Support PCIe extended config registers

FSL PCIe block has extended cfg registers in the 100 and 400 range.
For example, to read the LTSSM register: pci display <busn>.0 404 1

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>

diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c
index d7be0810f57ae0cd695cdf08ffc94f2c90c59151..a8220fb4117c2ac8de84da417814c051caad3254 100644 (file)
--- a/drivers/pci_indirect.c
+++ b/drivers/pci_indirect.c
@@ -45,7 +45,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose,             \
        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
        return 0;                                                        \
 }
-#elif defined(CONFIG_E500)
+#elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)                        \
 static int                                                               \
 indirect_##rw##_config_##size(struct pci_controller *hose,               \
@@ -55,7 +55,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose,               \
        b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);           \
        b = b - hose->first_busno;                                       \
        dev = PCI_BDF(b, d, f);                                          \
-       *(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000;          \
+       *(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \
        sync();                                                          \
        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
        return 0;                                                        \