sunxi: OLinuXino Lime A20 boards: Use 384 MHz DRAM clock
authorJosh Marshall <josh.marshall@tecevo.com>
Fri, 30 Sep 2016 05:19:58 +0000 (15:19 +1000)
committerHans de Goede <hdegoede@redhat.com>
Mon, 10 Oct 2016 07:24:00 +0000 (09:24 +0200)
We have a number of OlinuXino Lime2 boards (both NAND and eMMC versions)
which were experiencing sporadic hangs. After testing with some heavy
benchmarking and help from the Armbian forum, it was pinned down as the
DRAM settings for the board. The default is 480MHz, but this is unstable,
and even the build instructions from the vendor Olimex themselves say to
set the DRAM clock to 384. See line 96 at:
https://github.com/OLIMEX/OLINUXINO/blob/master/SOFTWARE/A20/A20-build-3.4.103-release-2/BUILD_DESCRIPTION_A20_Olimex_kernel_3.4.103%2B_Jessie_rel_2.txt

Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
configs/A20-OLinuXino-Lime2_defconfig
configs/A20-OLinuXino-Lime_defconfig

index 56886226df98744bcb69beaa1ebd98be560840c6..4751fe053332be1753b103afb95a984d7b019fff 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
index c4f6e1a9a2c5b57f4632de04b932335a80465385..024dc2d8a76cebd4e8069ac5960f1f644d150e71 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set