cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
-config SECURE_BOOT
- bool "Secure Boot"
+config NXP_ESBC
+ bool "NXP_ESBC"
help
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
Enable the EMC2305 fan controller for configuration of fan
speed.
-config SECURE_BOOT
- bool "Secure Boot"
+config NXP_ESBC
+ bool "NXP_ESBC"
help
Enable Freescale Secure Boot feature
void spl_board_init(void)
{
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
config CHAIN_OF_TRUST
- depends on !FIT_SIGNATURE && SECURE_BOOT
+ depends on !FIT_SIGNATURE && NXP_ESBC
imply CMD_BLOB
imply CMD_HASH if ARM
select FSL_CAAM
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
-ifdef CONFIG_SECURE_BOOT
+ifdef CONFIG_NXP_ESBC
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
endif
obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
init_final_memctl_regs();
#endif
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
* SMMU must be reset in bypass mode.
int board_init(void)
{
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
ppa_init();
#endif
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_AHCI=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_LS1012ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_TARGET_LS1028ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_AHCI=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_SYS_TEXT_BASE=0x20100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_SYS_TEXT_BASE=0x20100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_TEXT_BASE=0x80400000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SYS_TEXT_BASE=0x30100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_AHCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SYS_TEXT_BASE=0x30100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_AHCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SYS_TEXT_BASE=0x20100000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
CONFIG_EMC2305=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image.
*/
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
-#endif /* ifdef CONFIG_SECURE_BOOT */
+#endif /* ifdef CONFIG_NXP_ESBC */
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#include <asm/fsl_secure_boot.h>
#endif
#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
* HDR would be appended at end of image and copied to DDR along
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN 0x100000
-#endif /* ifdef CONFIG_SECURE_BOOT */
+#endif /* ifdef CONFIG_NXP_ESBC */
#endif
/* NAND SPL */
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
-#endif /* ifdef CONFIG_SECURE_BOOT */
+#endif /* ifdef CONFIG_NXP_ESBC */
#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
* HDR would be appended at end of image and copied to DDR along
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN 0x100000
-#endif /* ifdef CONFIG_SECURE_BOOT */
+#endif /* ifdef CONFIG_NXP_ESBC */
#endif
#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
* HDR would be appended at end of image and copied to DDR along
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN 0x100000
-#endif /* ifdef CONFIG_SECURE_BOOT */
+#endif /* ifdef CONFIG_NXP_ESBC */
#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
/* Initial environment variables */
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
"fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
"mcmemsize=0x70000000 \0"
-#else /* if !(CONFIG_SECURE_BOOT) */
+#else /* if !(CONFIG_NXP_ESBC) */
#ifdef CONFIG_TFABOOT
#define QSPI_MC_INIT_CMD \
"sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
"mcmemsize=0x70000000 \0"
#endif
#endif /* CONFIG_TFABOOT */
-#endif /* CONFIG_SECURE_BOOT */
+#endif /* CONFIG_NXP_ESBC */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x80100000\0" \
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
#endif /* CONFIG_TFABOOT */
-#endif /* CONFIG_SECURE_BOOT */
+#endif /* CONFIG_NXP_ESBC */
#ifdef CONFIG_TFABOOT
#define SD_BOOTCOMMAND \