source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
+source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/broadcom/Kconfig"
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON) += meson/
obj-$(CONFIG_PINCTRL_MTK) += mediatek/
+obj-$(CONFIG_PINCTRL_MSCC) += mscc/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config PINCTRL_MSCC
+ bool
+
+config PINCTRL_MSCC_OCELOT
+ depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi ocelot family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi ocelot SoCs.
+
+config PINCTRL_MSCC_LUTON
+ depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi luton family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi luton SoCs.
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-y += mscc-common.o
+obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
+obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <alexandre.belloni@free-electrons.com>
+ * Author: <gregory.clement@bootlin.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include "mscc-common.h"
+
+#define MSCC_GPIO_OUT_SET 0x0
+#define MSCC_GPIO_OUT_CLR 0x4
+#define MSCC_GPIO_OUT 0x8
+#define MSCC_GPIO_IN 0xc
+#define MSCC_GPIO_OE 0x10
+#define MSCC_GPIO_INTR 0x14
+#define MSCC_GPIO_INTR_ENA 0x18
+#define MSCC_GPIO_INTR_IDENT 0x1c
+#define MSCC_GPIO_ALT0 0x20
+#define MSCC_GPIO_ALT1 0x24
+
+static int mscc_get_functions_count(struct udevice *dev)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_func;
+}
+
+static const char *mscc_get_function_name(struct udevice *dev,
+ unsigned int function)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->function_names[function];
+}
+
+static int mscc_pin_function_idx(unsigned int pin, unsigned int function,
+ const struct mscc_pin_data *mscc_pins)
+{
+ struct mscc_pin_caps *p = mscc_pins[pin].drv_data;
+ int i;
+
+ for (i = 0; i < MSCC_FUNC_PER_PIN; i++) {
+ if (function == p->functions[i])
+ return i;
+ }
+
+ return -1;
+}
+
+static int mscc_pinmux_set_mux(struct udevice *dev,
+ unsigned int pin_selector, unsigned int selector)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+ struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
+ int f;
+
+ f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
+ if (f < 0)
+ return -EINVAL;
+ /*
+ * f is encoded on two bits.
+ * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
+ * ALT1
+ * This is racy because both registers can't be updated at the same time
+ * but it doesn't matter much for now.
+ */
+ if (f & BIT(0))
+ setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
+ else
+ clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
+
+ if (f & BIT(1))
+ setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
+ else
+ clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
+
+ return 0;
+}
+
+static int mscc_pctl_get_groups_count(struct udevice *dev)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_pins;
+}
+
+static const char *mscc_pctl_get_group_name(struct udevice *dev,
+ unsigned int group)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->mscc_pins[group].name;
+}
+
+static int mscc_create_group_func_map(struct udevice *dev,
+ struct mscc_pinctrl *info)
+{
+ u16 pins[info->num_pins];
+ int f, npins, i;
+
+ for (f = 0; f < info->num_func; f++) {
+ for (npins = 0, i = 0; i < info->num_pins; i++) {
+ if (mscc_pin_function_idx(i, f, info->mscc_pins) >= 0)
+ pins[npins++] = i;
+ }
+
+ info->func[f].ngroups = npins;
+ info->func[f].groups = devm_kzalloc(dev, npins *
+ sizeof(char *), GFP_KERNEL);
+ if (!info->func[f].groups)
+ return -ENOMEM;
+
+ for (i = 0; i < npins; i++)
+ info->func[f].groups[i] = info->mscc_pins[pins[i]].name;
+ }
+
+ return 0;
+}
+
+static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info)
+{
+ int ret;
+
+ ret = mscc_create_group_func_map(dev, info);
+ if (ret) {
+ dev_err(dev, "Unable to create group func map.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mscc_gpio_get(struct udevice *dev, unsigned int offset)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+ unsigned int val;
+
+ val = readl(info->regs + MSCC_GPIO_IN);
+
+ return !!(val & BIT(offset));
+}
+
+static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+
+ if (value)
+ writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET);
+ else
+ writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR);
+
+ return 0;
+}
+
+static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+ unsigned int val;
+
+ val = readl(info->regs + MSCC_GPIO_OE);
+
+ return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+
+ clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
+
+ return 0;
+}
+
+static int mscc_gpio_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+
+ setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
+
+ return mscc_gpio_set(dev, offset, value);
+}
+
+const struct dm_gpio_ops mscc_gpio_ops = {
+ .set_value = mscc_gpio_set,
+ .get_value = mscc_gpio_get,
+ .get_function = mscc_gpio_get_direction,
+ .direction_input = mscc_gpio_direction_input,
+ .direction_output = mscc_gpio_direction_output,
+};
+
+const struct pinctrl_ops mscc_pinctrl_ops = {
+ .get_pins_count = mscc_pctl_get_groups_count,
+ .get_pin_name = mscc_pctl_get_group_name,
+ .get_functions_count = mscc_get_functions_count,
+ .get_function_name = mscc_get_function_name,
+ .pinmux_set = mscc_pinmux_set_mux,
+ .set_state = pinctrl_generic_set_state,
+};
+
+int mscc_pinctrl_probe(struct udevice *dev, int num_func,
+ const struct mscc_pin_data *mscc_pins, int num_pins,
+ char *const *function_names)
+{
+ struct mscc_pinctrl *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->regs = dev_remap_addr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func),
+ GFP_KERNEL);
+ priv->num_func = num_func;
+ priv->mscc_pins = mscc_pins;
+ priv->num_pins = num_pins;
+ priv->function_names = function_names;
+ ret = mscc_pinctrl_register(dev, priv);
+
+ return ret;
+}
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <alexandre.belloni@free-electrons.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#define MSCC_FUNC_PER_PIN 4
+
+struct mscc_pin_caps {
+ unsigned int pin;
+ unsigned char functions[MSCC_FUNC_PER_PIN];
+};
+
+struct mscc_pin_data {
+ const char *name;
+ struct mscc_pin_caps *drv_data;
+};
+
+#define MSCC_P(p, f0, f1, f2) \
+static struct mscc_pin_caps mscc_pin_##p = { \
+ .pin = p, \
+ .functions = { \
+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
+ }, \
+}
+
+struct mscc_pmx_func {
+ const char **groups;
+ unsigned int ngroups;
+};
+
+struct mscc_pinctrl {
+ struct udevice *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *regs;
+ struct mscc_pmx_func *func;
+ int num_func;
+ const struct mscc_pin_data *mscc_pins;
+ int num_pins;
+ char * const *function_names;
+};
+
+int mscc_pinctrl_probe(struct udevice *dev, int num_func,
+ const struct mscc_pin_data *mscc_pins, int num_pins,
+ char * const *function_names);
+const struct pinctrl_ops mscc_pinctrl_ops;
+
+const struct dm_gpio_ops mscc_gpio_ops;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <gregory.clement@bootlin.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_SIO,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_PHY_LED,
+ FUNC_EXT_IRQ,
+ FUNC_SFP,
+ FUNC_SI,
+ FUNC_PWM,
+ FUNC_UART,
+ FUNC_MAX
+};
+
+static char * const luton_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_SIO] = "sio",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_PHY_LED] = "phy_led",
+ [FUNC_EXT_IRQ] = "ext_irq",
+ [FUNC_SFP] = "sfp",
+ [FUNC_SI] = "si",
+ [FUNC_PWM] = "pwm",
+ [FUNC_UART] = "uart",
+};
+
+MSCC_P(0, SIO, NONE, NONE);
+MSCC_P(1, SIO, NONE, NONE);
+MSCC_P(2, SIO, NONE, NONE);
+MSCC_P(3, SIO, NONE, NONE);
+MSCC_P(4, TACHO, NONE, NONE);
+MSCC_P(5, TWI, PHY_LED, NONE);
+MSCC_P(6, TWI, PHY_LED, NONE);
+MSCC_P(7, NONE, PHY_LED, NONE);
+MSCC_P(8, EXT_IRQ, PHY_LED, NONE);
+MSCC_P(9, EXT_IRQ, PHY_LED, NONE);
+MSCC_P(10, SFP, PHY_LED, NONE);
+MSCC_P(11, SFP, PHY_LED, NONE);
+MSCC_P(12, SFP, PHY_LED, NONE);
+MSCC_P(13, SFP, PHY_LED, NONE);
+MSCC_P(14, SI, PHY_LED, NONE);
+MSCC_P(15, SI, PHY_LED, NONE);
+MSCC_P(16, SI, PHY_LED, NONE);
+MSCC_P(17, SFP, PHY_LED, NONE);
+MSCC_P(18, SFP, PHY_LED, NONE);
+MSCC_P(19, SFP, PHY_LED, NONE);
+MSCC_P(20, SFP, PHY_LED, NONE);
+MSCC_P(21, SFP, PHY_LED, NONE);
+MSCC_P(22, SFP, PHY_LED, NONE);
+MSCC_P(23, SFP, PHY_LED, NONE);
+MSCC_P(24, SFP, PHY_LED, NONE);
+MSCC_P(25, SFP, PHY_LED, NONE);
+MSCC_P(26, SFP, PHY_LED, NONE);
+MSCC_P(27, SFP, PHY_LED, NONE);
+MSCC_P(28, SFP, PHY_LED, NONE);
+MSCC_P(29, PWM, NONE, NONE);
+MSCC_P(30, UART, NONE, NONE);
+MSCC_P(31, UART, NONE, NONE);
+
+#define LUTON_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data luton_pins[] = {
+ LUTON_PIN(0),
+ LUTON_PIN(1),
+ LUTON_PIN(2),
+ LUTON_PIN(3),
+ LUTON_PIN(4),
+ LUTON_PIN(5),
+ LUTON_PIN(6),
+ LUTON_PIN(7),
+ LUTON_PIN(8),
+ LUTON_PIN(9),
+ LUTON_PIN(10),
+ LUTON_PIN(11),
+ LUTON_PIN(12),
+ LUTON_PIN(13),
+ LUTON_PIN(14),
+ LUTON_PIN(15),
+ LUTON_PIN(16),
+ LUTON_PIN(17),
+ LUTON_PIN(18),
+ LUTON_PIN(19),
+ LUTON_PIN(20),
+ LUTON_PIN(21),
+ LUTON_PIN(22),
+ LUTON_PIN(23),
+ LUTON_PIN(24),
+ LUTON_PIN(25),
+ LUTON_PIN(26),
+ LUTON_PIN(27),
+ LUTON_PIN(28),
+ LUTON_PIN(29),
+ LUTON_PIN(30),
+ LUTON_PIN(31),
+};
+
+static int luton_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "luton-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(luton_pins);
+
+ return 0;
+}
+
+static struct driver luton_gpio_driver = {
+ .name = "luton-gpio",
+ .id = UCLASS_GPIO,
+ .probe = luton_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+int luton_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
+ ARRAY_SIZE(luton_pins), luton_function_names);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &luton_gpio_driver, "luton-gpio", NULL,
+ dev_of_offset(dev), NULL);
+
+ return 0;
+}
+
+static const struct udevice_id luton_pinctrl_of_match[] = {
+ {.compatible = "mscc,luton-pinctrl"},
+ {},
+};
+
+U_BOOT_DRIVER(luton_pinctrl) = {
+ .name = "luton-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(luton_pinctrl_of_match),
+ .probe = luton_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <alexandre.belloni@free-electrons.com>
+ * Author: <gregory.clement@bootlin.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0_IN,
+ FUNC_IRQ0_OUT,
+ FUNC_IRQ1_IN,
+ FUNC_IRQ1_OUT,
+ FUNC_MIIM1,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RECO_CLK0,
+ FUNC_RECO_CLK1,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SG0,
+ FUNC_SI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MAX
+};
+
+static char * const ocelot_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0_IN] = "irq0_in",
+ [FUNC_IRQ0_OUT] = "irq0_out",
+ [FUNC_IRQ1_IN] = "irq1_in",
+ [FUNC_IRQ1_OUT] = "irq1_out",
+ [FUNC_MIIM1] = "miim1",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RECO_CLK0] = "reco_clk0",
+ [FUNC_RECO_CLK1] = "reco_clk1",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SG0] = "sg0",
+ [FUNC_SI] = "si",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI_SCL_M] = "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2] = "uart2",
+};
+
+MSCC_P(0, SG0, NONE, NONE);
+MSCC_P(1, SG0, NONE, NONE);
+MSCC_P(2, SG0, NONE, NONE);
+MSCC_P(3, SG0, NONE, NONE);
+MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI);
+MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
+MSCC_P(6, UART, TWI_SCL_M, NONE);
+MSCC_P(7, UART, TWI_SCL_M, NONE);
+MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT);
+MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT);
+MSCC_P(10, PTP2, TWI_SCL_M, SFP0);
+MSCC_P(11, PTP3, TWI_SCL_M, SFP1);
+MSCC_P(12, UART2, TWI_SCL_M, SFP2);
+MSCC_P(13, UART2, TWI_SCL_M, SFP3);
+MSCC_P(14, MIIM1, TWI_SCL_M, SFP4);
+MSCC_P(15, MIIM1, TWI_SCL_M, SFP5);
+MSCC_P(16, TWI, NONE, SI);
+MSCC_P(17, TWI, TWI_SCL_M, SI);
+MSCC_P(18, PTP0, TWI_SCL_M, NONE);
+MSCC_P(19, PTP1, TWI_SCL_M, NONE);
+MSCC_P(20, RECO_CLK0, TACHO, NONE);
+MSCC_P(21, RECO_CLK1, PWM, NONE);
+
+#define OCELOT_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data ocelot_pins[] = {
+ OCELOT_PIN(0),
+ OCELOT_PIN(1),
+ OCELOT_PIN(2),
+ OCELOT_PIN(3),
+ OCELOT_PIN(4),
+ OCELOT_PIN(5),
+ OCELOT_PIN(6),
+ OCELOT_PIN(7),
+ OCELOT_PIN(8),
+ OCELOT_PIN(9),
+ OCELOT_PIN(10),
+ OCELOT_PIN(11),
+ OCELOT_PIN(12),
+ OCELOT_PIN(13),
+ OCELOT_PIN(14),
+ OCELOT_PIN(15),
+ OCELOT_PIN(16),
+ OCELOT_PIN(17),
+ OCELOT_PIN(18),
+ OCELOT_PIN(19),
+ OCELOT_PIN(20),
+ OCELOT_PIN(21),
+};
+
+static int ocelot_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "ocelot-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins);
+
+ return 0;
+}
+
+static struct driver ocelot_gpio_driver = {
+ .name = "ocelot-gpio",
+ .id = UCLASS_GPIO,
+ .probe = ocelot_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+int ocelot_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
+ ARRAY_SIZE(ocelot_pins),
+ ocelot_function_names);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL,
+ dev_of_offset(dev), NULL);
+
+ return ret;
+}
+
+static const struct udevice_id ocelot_pinctrl_of_match[] = {
+ {.compatible = "mscc,ocelot-pinctrl"},
+ {},
+};
+
+U_BOOT_DRIVER(ocelot_pinctrl) = {
+ .name = "ocelot-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ocelot_pinctrl_of_match),
+ .probe = ocelot_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
projects / oweals / u-boot.git / commitdiff