armada-xp-theadorable.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
- uniphier-ph1-ld11-ref.dtb \
- uniphier-ph1-ld20-ref.dtb \
- uniphier-ph1-ld4-ref.dtb \
- uniphier-ph1-ld6b-ref.dtb \
- uniphier-ph1-pro4-ace.dtb \
- uniphier-ph1-pro4-ref.dtb \
- uniphier-ph1-pro4-sanji.dtb \
- uniphier-ph1-pro5-4kbox.dtb \
- uniphier-ph1-sld3-ref.dtb \
- uniphier-ph1-sld8-ref.dtb \
- uniphier-proxstream2-gentil.dtb \
- uniphier-proxstream2-vodka.dtb
+ uniphier-ld11-ref.dtb \
+ uniphier-ld20-ref.dtb \
+ uniphier-ld4-ref.dtb \
+ uniphier-ld6b-ref.dtb \
+ uniphier-pro4-ace.dtb \
+ uniphier-pro4-ref.dtb \
+ uniphier-pro4-sanji.dtb \
+ uniphier-pro5-4kbox.dtb \
+ uniphier-pxs2-gentil.dtb \
+ uniphier-pxs2-vodka.dtb \
+ uniphier-sld3-ref.dtb \
+ uniphier-sld8-ref.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
/*
* Device Tree Source commonly used by UniPhier ARM SoCs
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton.dtsi"
/ {
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
refclk: ref {
#clock-cells = <0>;
--- /dev/null
+/*
+ * Device Tree Source for UniPhier LD11 Reference Board
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld11.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier LD11 Reference Board";
+ compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_system_bus {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier LD11 SoC
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
+
+/ {
+ compatible = "socionext,uniphier-ld11";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000000>;
+ };
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 4>,
+ <1 14 4>,
+ <1 11 4>,
+ <1 10 4>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ u-boot,dm-pre-reloc;
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <58820000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <58820000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <58820000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <58820000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-ld11-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-ld11-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 243 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 244 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 245 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ mioctrl@5b3e0000 {
+ compatible = "socionext,uniphier-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x5b3e0000 0x800>;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-ld11-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-ld11-mio-reset";
+ #reset-cells = <1>;
+ resets = <&sys_rst 7>;
+ };
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-ld11-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ gic: interrupt-controller@5fe00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x5fe00000 0x10000>, /* GICD */
+ <0x5fe40000 0x80000>; /* GICR */
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 4>;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-ld11-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-ld11-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-ld11-reset";
+ #reset-cells = <1>;
+ };
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for UniPhier LD20 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld20.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier LD20 Reference Board";
+ compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xc0000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_system_bus {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier LD20 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
+
+/ {
+ compatible = "socionext,uniphier-ld20";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ core1 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000000>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000000>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000000>;
+ };
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 4>,
+ <1 14 4>,
+ <1 11 4>,
+ <1 10 4>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ u-boot,dm-pre-reloc;
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <58820000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <58820000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <58820000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <58820000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-ld20-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-ld20-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-ld20-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-ld20-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x800>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host";
+ resets = <&mio_rst 0>;
+ bus-width = <4>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-ld20-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ gic: interrupt-controller@5fe00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x5fe00000 0x10000>, /* GICD */
+ <0x5fe80000 0x80000>; /* GICR */
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 4>;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-ld20-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-ld20-reset";
+ #reset-cells = <1>;
+ };
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for UniPhier LD4 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld4.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier LD4 Reference Board";
+ compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+ðsc {
+ interrupts = <0 49 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&serial3 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier LD4 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "uniphier-common32.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-ld4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ iobus_clk: iobus_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ };
+};
+
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(512 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port16x: gpio@55000088 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000088 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ bus-width = <4>;
+ };
+
+ emmc: sdhc@5a500000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a500000 0x200>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_emmc>;
+ pinctrl-1 = <&pinctrl_emmc_1v8>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ bus-width = <8>;
+ non-removable;
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ aidet@61830000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x61830000 0x200>;
+ };
+};
+
+&refclk {
+ clock-frequency = <24576000>;
+};
+
+&serial0 {
+ clock-frequency = <36864000>;
+};
+
+&serial1 {
+ clock-frequency = <36864000>;
+};
+
+&serial2 {
+ clock-frequency = <36864000>;
+};
+
+&serial3 {
+ interrupts = <0 29 4>;
+ clock-frequency = <36864000>;
+};
+
+&mio_clk {
+ compatible = "socionext,uniphier-ld4-mio-clock";
+};
+
+&mio_rst {
+ compatible = "socionext,uniphier-ld4-mio-reset";
+};
+
+&peri_clk {
+ compatible = "socionext,uniphier-ld4-peri-clock";
+};
+
+&peri_rst {
+ compatible = "socionext,uniphier-ld4-peri-reset";
+};
+
+&pinctrl {
+ compatible = "socionext,uniphier-ld4-pinctrl";
+};
+
+&sys_clk {
+ compatible = "socionext,uniphier-ld4-clock";
+};
+
+&sys_rst {
+ compatible = "socionext,uniphier-ld4-reset";
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier LD6b Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld6b.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier LD6b Reference Board";
+ compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+ðsc {
+ interrupts = <0 52 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier LD6b SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/*
+ * LD6b consists of two silicon dies: D-chip and A-chip.
+ * The D-chip (digital chip) is the same as the PXs2 die.
+ * Reuse the PXs2 device tree with some properties overridden.
+ */
+/include/ "uniphier-pxs2.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-ld6b";
+};
+
+/* UART3 unavailable: the pads are not wired to the package balls */
+&serial3 {
+ status = "disabled";
+};
+
+/*
+ * LD6b and PXs2 have completely different packages,
+ * which makes the pinctrl driver unshareable.
+ */
+&pinctrl {
+ compatible = "socionext,uniphier-ld6b-pinctrl";
+};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-LD11 Reference Board
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-ld11.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-LD11 Reference Board";
- compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11";
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- };
-
- memory {
- device_type = "memory";
- reg = <0 0x80000000 0 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-ðsc {
- interrupts = <0 48 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_system_bus {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-LD11 SoC
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
-
-/ {
- compatible = "socionext,ph1-ld11";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0 0x000>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0 0x001>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
- };
-
- clocks {
- refclk: ref {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 4>,
- <1 14 4>,
- <1 11 4>,
- <1 10 4>;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0xffffffff>;
- u-boot,dm-pre-reloc;
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&peri_clk 0>;
- clock-frequency = <58820000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&peri_clk 1>;
- clock-frequency = <58820000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- clocks = <&peri_clk 2>;
- clock-frequency = <58820000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- clocks = <&peri_clk 3>;
- clock-frequency = <58820000>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- status = "disabled";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_system_bus>;
- };
-
- smpctrl@59800000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- perictrl@59820000 {
- compatible = "socionext,uniphier-perictrl",
- "simple-mfd", "syscon";
- reg = <0x59820000 0x200>;
-
- peri_clk: clock {
- compatible = "socionext,uniphier-ld11-peri-clock";
- #clock-cells = <1>;
- };
-
- peri_rst: reset {
- compatible = "socionext,uniphier-ld11-peri-reset";
- #reset-cells = <1>;
- };
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 243 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 244 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 245 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
- };
-
- mioctrl@5b3e0000 {
- compatible = "socionext,uniphier-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x5b3e0000 0x800>;
-
- mio_clk: clock {
- compatible = "socionext,uniphier-ld11-mio-clock";
- #clock-cells = <1>;
- };
-
- mio_rst: reset {
- compatible = "socionext,uniphier-ld11-mio-reset";
- #reset-cells = <1>;
- resets = <&sys_rst 7>;
- };
- };
-
- soc-glue@5f800000 {
- compatible = "socionext,uniphier-soc-glue",
- "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
-
- pinctrl: pinctrl {
- compatible = "socionext,uniphier-ld11-pinctrl";
- u-boot,dm-pre-reloc;
- };
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- gic: interrupt-controller@5fe00000 {
- compatible = "arm,gic-v3";
- reg = <0x5fe00000 0x10000>, /* GICD */
- <0x5fe40000 0x80000>; /* GICR */
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <1 9 4>;
- };
-
- sysctrl@61840000 {
- compatible = "socionext,uniphier-ld11-sysctrl",
- "simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
-
- sys_clk: clock {
- compatible = "socionext,uniphier-ld11-clock";
- #clock-cells = <1>;
- };
-
- sys_rst: reset {
- compatible = "socionext,uniphier-ld11-reset";
- #reset-cells = <1>;
- };
- };
- };
-};
-
-/include/ "uniphier-pinctrl.dtsi"
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-LD20 Reference Board
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-ld20.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-LD20 Reference Board";
- compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- };
-
- memory {
- device_type = "memory";
- reg = <0 0x80000000 0 0xc0000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-ðsc {
- interrupts = <0 48 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_system_bus {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-LD20 SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
-
-/ {
- compatible = "socionext,ph1-ld20";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&cpu2>;
- };
- core1 {
- cpu = <&cpu3>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0 0x000>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0 0x001>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
-
- cpu2: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0 0x100>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
-
- cpu3: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0 0x101>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
- };
-
- clocks {
- refclk: ref {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 4>,
- <1 14 4>,
- <1 11 4>,
- <1 10 4>;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0xffffffff>;
- u-boot,dm-pre-reloc;
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&peri_clk 0>;
- clock-frequency = <58820000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&peri_clk 1>;
- clock-frequency = <58820000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- clocks = <&peri_clk 2>;
- clock-frequency = <58820000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- clocks = <&peri_clk 3>;
- clock-frequency = <58820000>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- status = "disabled";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_system_bus>;
- };
-
- smpctrl@59800000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- mioctrl@59810000 {
- compatible = "socionext,uniphier-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
-
- mio_clk: clock {
- compatible = "socionext,uniphier-ld20-mio-clock";
- #clock-cells = <1>;
- };
-
- mio_rst: reset {
- compatible = "socionext,uniphier-ld20-mio-reset";
- #reset-cells = <1>;
- };
- };
-
- perictrl@59820000 {
- compatible = "socionext,uniphier-perictrl",
- "simple-mfd", "syscon";
- reg = <0x59820000 0x200>;
-
- peri_clk: clock {
- compatible = "socionext,uniphier-ld20-peri-clock";
- #clock-cells = <1>;
- };
-
- peri_rst: reset {
- compatible = "socionext,uniphier-ld20-peri-reset";
- #reset-cells = <1>;
- };
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sd>;
- clocks = <&mio_clk 0>;
- bus-width = <4>;
- };
-
- soc-glue@5f800000 {
- compatible = "socionext,uniphier-soc-glue",
- "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
-
- pinctrl: pinctrl {
- compatible = "socionext,uniphier-ld20-pinctrl";
- u-boot,dm-pre-reloc;
- };
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- gic: interrupt-controller@5fe00000 {
- compatible = "arm,gic-v3";
- reg = <0x5fe00000 0x10000>, /* GICD */
- <0x5fe80000 0x80000>; /* GICR */
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <1 9 4>;
- };
-
- sysctrl@61840000 {
- compatible = "socionext,uniphier-sysctrl",
- "simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
-
- sys_clk: clock {
- compatible = "socionext,uniphier-ld20-clock";
- #clock-cells = <1>;
- };
-
- sys_rst: reset {
- compatible = "socionext,uniphier-ld20-reset";
- #reset-cells = <1>;
- };
- };
- };
-};
-
-/include/ "uniphier-pinctrl.dtsi"
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-LD4 Reference Board
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-ld4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-LD4 Reference Board";
- compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- };
-};
-
-ðsc {
- interrupts = <0 49 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&serial3 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-LD4 SoC
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,ph1-ld4";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- iobus_clk: iobus_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(512 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
-
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio_clk 0>;
- bus-width = <4>;
- };
-
- emmc: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_emmc>;
- pinctrl-1 = <&pinctrl_emmc_1v8>;
- clocks = <&mio_clk 1>;
- bus-width = <8>;
- non-removable;
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
- };
-
- aidet@61830000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x61830000 0x200>;
- };
-};
-
-&refclk {
- clock-frequency = <24576000>;
-};
-
-&serial0 {
- clock-frequency = <36864000>;
-};
-
-&serial1 {
- clock-frequency = <36864000>;
-};
-
-&serial2 {
- clock-frequency = <36864000>;
-};
-
-&serial3 {
- interrupts = <0 29 4>;
- clock-frequency = <36864000>;
-};
-
-&mio_clk {
- compatible = "socionext,uniphier-ld4-mio-clock";
-};
-
-&mio_rst {
- compatible = "socionext,uniphier-ld4-mio-reset";
-};
-
-&peri_clk {
- compatible = "socionext,uniphier-ld4-peri-clock";
-};
-
-&peri_rst {
- compatible = "socionext,uniphier-ld4-peri-reset";
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-ld4-pinctrl";
-};
-
-&sys_clk {
- compatible = "socionext,uniphier-ld4-clock";
-};
-
-&sys_rst {
- compatible = "socionext,uniphier-ld4-reset";
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-LD6b Reference Board
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-ld6b.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-LD6b Reference Board";
- compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-ðsc {
- interrupts = <0 52 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-LD6b SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/*
- * PH1-LD6b consists of two silicon dies: D-chip and A-chip.
- * The D-chip (digital chip) is the same as the ProXstream2 die.
- * Reuse the ProXstream2 device tree with some properties overridden.
- */
-/include/ "uniphier-proxstream2.dtsi"
-
-/ {
- compatible = "socionext,ph1-ld6b";
-};
-
-/* UART3 unavailable: the pads are not wired to the package balls */
-&serial3 {
- status = "disabled";
-};
-
-/*
- * PH1-LD6b and ProXstream2 have completely different packages,
- * which makes the pinctrl driver unshareable.
- */
-&pinctrl {
- compatible = "socionext,uniphier-ld6b-pinctrl";
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-Pro4 Ace Board
- *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
-
-/ {
- model = "UniPhier PH1-Pro4 Ace Board";
- compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- eeprom {
- compatible = "24c64", "i2c-eeprom";
- reg = <0x54>;
- u-boot,i2c-offset-len = <2>;
- };
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-Pro4 Reference Board
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-Pro4 Reference Board";
- compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- usb0 = &usb0;
- };
-};
-
-ðsc {
- interrupts = <0 50 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&sd1 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-Pro4 Sanji Board
- *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
-
-/ {
- model = "UniPhier PH1-Pro4 Sanji Board";
- compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- eeprom {
- compatible = "24c64", "i2c-eeprom";
- reg = <0x54>;
- u-boot,i2c-offset-len = <2>;
- };
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&mio_clk {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-Pro4 SoC
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,ph1-pro4";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <73728000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(768 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port17x: gpio@550000a0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port18x: gpio@550000a8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port19x: gpio@550000b0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port20x: gpio@550000b8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port21x: gpio@550000c0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port22x: gpio@550000c8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port23x: gpio@550000d0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port24x: gpio@550000d8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port25x: gpio@550000e0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port26x: gpio@550000e8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port27x: gpio@550000f0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port28x: gpio@550000f8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port29x: gpio@55000100 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000100 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port30x: gpio@55000108 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000108 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- /* i2c4 does not exist */
-
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio_clk 0>;
- bus-width = <4>;
- };
-
- emmc: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_emmc>;
- pinctrl-1 = <&pinctrl_emmc_1v8>;
- clocks = <&mio_clk 1>;
- bus-width = <8>;
- non-removable;
- };
-
- sd1: sdhc@5a600000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a600000 0x200>;
- interrupts = <0 85 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd1>;
- pinctrl-1 = <&pinctrl_sd1_1v8>;
- clocks = <&mio_clk 2>;
- bus-width = <4>;
- };
-
- usb2: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
- };
-
- usb3: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- interrupts = <0 134 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- };
-
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- interrupts = <0 137 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- };
-};
-
-&refclk {
- clock-frequency = <25000000>;
-};
-
-&serial0 {
- clock-frequency = <73728000>;
-};
-
-&serial1 {
- clock-frequency = <73728000>;
-};
-
-&serial2 {
- clock-frequency = <73728000>;
-};
-
-&serial3 {
- clock-frequency = <73728000>;
-};
-
-&mio_clk {
- compatible = "socionext,uniphier-pro4-mio-clock";
-};
-
-&mio_rst {
- compatible = "socionext,uniphier-pro4-mio-reset";
-};
-
-&peri_clk {
- compatible = "socionext,uniphier-pro4-peri-clock";
-};
-
-&peri_rst {
- compatible = "socionext,uniphier-pro4-peri-reset";
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-pro4-pinctrl";
-};
-
-&sys_clk {
- compatible = "socionext,uniphier-pro4-clock";
-};
-
-&sys_rst {
- compatible = "socionext,uniphier-pro4-reset";
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-pro5.dtsi"
-
-/ {
- model = "UniPhier PH1-Pro5 4KBOX Board";
- compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial1:115200n8";
- };
-
- aliases {
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial1 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-Pro5 SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,ph1-pro5";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
- interrupts = <0 190 4>, <0 191 4>;
- cache-unified;
- cache-size = <(2 * 1024 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
-
- l3: l3-cache@500c8000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(2 * 1024 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <256>;
- cache-level = <3>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port17x: gpio@550000a0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port18x: gpio@550000a8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port19x: gpio@550000b0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port20x: gpio@550000b8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port21x: gpio@550000c0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port22x: gpio@550000c8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port23x: gpio@550000d0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port24x: gpio@550000d8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port25x: gpio@550000e0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port26x: gpio@550000e8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port27x: gpio@550000f0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port28x: gpio@550000f8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port29x: gpio@55000100 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000100 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port30x: gpio@55000108 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000108 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- /* i2c4 does not exist */
-
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- emmc: sdhc@68400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x68400000 0x800>;
- interrupts = <0 78 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_emmc>;
- clocks = <&mio_clk 1>;
- bus-width = <8>;
- non-removable;
- };
-
- sd: sdhc@68800000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x68800000 0x800>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio_clk 0>;
- bus-width = <4>;
- };
-
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- interrupts = <0 134 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- };
-
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- interrupts = <0 137 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
- };
-};
-
-&refclk {
- clock-frequency = <20000000>;
-};
-
-&serial0 {
- clock-frequency = <73728000>;
-};
-
-&serial1 {
- clock-frequency = <73728000>;
-};
-
-&serial2 {
- clock-frequency = <73728000>;
-};
-
-&serial3 {
- clock-frequency = <73728000>;
-};
-
-&mio_clk {
- compatible = "socionext,uniphier-pro5-mio-clock";
-};
-
-&mio_rst {
- compatible = "socionext,uniphier-pro5-mio-reset";
-};
-
-&peri_clk {
- compatible = "socionext,uniphier-pro5-peri-clock";
-};
-
-&peri_rst {
- compatible = "socionext,uniphier-pro5-peri-reset";
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-pro5-pinctrl";
-};
-
-&sys_clk {
- compatible = "socionext,uniphier-pro5-clock";
-};
-
-&sys_rst {
- compatible = "socionext,uniphier-pro5-reset";
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-sLD3 Reference Board
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-sld3.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-sLD3 Reference Board";
- compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000
- 0xc0000000 0x20000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- };
-};
-
-ðsc {
- interrupts = <0 49 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-sLD3 SoC
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
- compatible = "socionext,ph1-sld3";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- };
- };
-
- clocks {
- refclk: ref {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24576000>;
- };
-
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- iobus_clk: iobus_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
- u-boot,dm-pre-reloc;
-
- timer@20000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x20000200 0x20>;
- interrupts = <1 11 0x304>;
- clocks = <&arm_timer_clk>;
- };
-
- timer@20000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x20000600 0x20>;
- interrupts = <1 13 0x304>;
- clocks = <&arm_timer_clk>;
- };
-
- intc: interrupt-controller@20001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x20001000 0x1000>,
- <0x20000100 0x100>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- clock-frequency = <36864000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clock-frequency = <36864000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- clock-frequency = <36864000>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c4: i2c@58600000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58600000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- smpctrl@59800000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- mioctrl@59810000 {
- compatible = "socionext,uniphier-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
- u-boot,dm-pre-reloc;
-
- mio_clk: clock {
- compatible = "socionext,uniphier-sld3-mio-clock";
- #clock-cells = <1>;
- u-boot,dm-pre-reloc;
- };
-
- mio_rst: reset {
- compatible = "socionext,uniphier-sld3-mio-reset";
- #reset-cells = <1>;
- };
- };
-
- emmc: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 78 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_emmc>;
- pinctrl-1 = <&pinctrl_emmc_1v8>;
- clocks = <&mio_clk 1>;
- bus-width = <8>;
- non-removable;
- };
-
- sd: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a500000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio_clk 0>;
- bus-width = <4>;
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
- };
-
- usb3: usb@5a830100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a830100 0x100>;
- interrupts = <0 83 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&mio_clk 7>, <&mio_clk 6>;
- };
-
- soc-glue@5f800000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
-
- pinctrl: pinctrl {
- compatible = "socionext,uniphier-sld3-pinctrl";
- u-boot,dm-pre-reloc;
- };
- };
-
- aidet@f1830000 {
- compatible = "simple-mfd", "syscon";
- reg = <0xf1830000 0x200>;
- };
-
- sysctrl@f1840000 {
- compatible = "socionext,uniphier-sysctrl",
- "simple-mfd", "syscon";
- reg = <0xf1840000 0x4000>;
-
- sys_clk: clock {
- compatible = "socionext,uniphier-sld3-clock";
- #clock-cells = <1>;
- };
-
- sys_rst: reset {
- compatible = "socionext,uniphier-sld3-reset";
- #reset-cells = <1>;
- };
- };
-
- nand: nand@f8000000 {
- compatible = "denali,denali-nand-dt";
- reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- };
- };
-};
-
-/include/ "uniphier-pinctrl.dtsi"
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-sLD8 Reference Board
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-sld8.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-sLD8 Reference Board";
- compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- };
-};
-
-ðsc {
- interrupts = <0 48 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&serial3 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier PH1-sLD8 SoC
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,ph1-sld8";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- iobus_clk: iobus_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(256 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
-
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio_clk 0>;
- bus-width = <4>;
- };
-
- emmc: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- interrupts = <0 78 4>;
- reg = <0x5a500000 0x200>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_emmc>;
- pinctrl-1 = <&pinctrl_emmc_1v8>;
- clocks = <&mio_clk 1>;
- bus-width = <8>;
- non-removable;
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
- };
-
- aidet@61830000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x61830000 0x200>;
- };
-};
-
-&refclk {
- clock-frequency = <25000000>;
-};
-
-&serial0 {
- clock-frequency = <80000000>;
-};
-
-&serial1 {
- clock-frequency = <80000000>;
-};
-
-&serial2 {
- clock-frequency = <80000000>;
-};
-
-&serial3 {
- interrupts = <0 29 4>;
- clock-frequency = <80000000>;
-};
-
-&mio_clk {
- compatible = "socionext,uniphier-sld8-mio-clock";
-};
-
-&mio_rst {
- compatible = "socionext,uniphier-sld8-mio-reset";
-};
-
-&peri_clk {
- compatible = "socionext,uniphier-sld8-peri-clock";
-};
-
-&peri_rst {
- compatible = "socionext,uniphier-sld8-peri-reset";
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-sld8-pinctrl";
-};
-
-&sys_clk {
- compatible = "socionext,uniphier-sld8-clock";
-};
-
-&sys_rst {
- compatible = "socionext,uniphier-sld8-reset";
-};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier Pro4 Ace Board
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-pro4.dtsi"
+
+/ {
+ model = "UniPhier Pro4 Ace Board";
+ compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
+ reg = <0x54>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier Pro4 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-pro4.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier Pro4 Reference Board";
+ compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ usb0 = &usb0;
+ };
+};
+
+ðsc {
+ interrupts = <0 50 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&sd1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier Pro4 Sanji Board
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-pro4.dtsi"
+
+/ {
+ model = "UniPhier Pro4 Sanji Board";
+ compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
+ reg = <0x54>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&mio_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier Pro4 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "uniphier-common32.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-pro4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ uart_clk: uart_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <73728000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+};
+
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(768 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port17x: gpio@550000a0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port18x: gpio@550000a8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port19x: gpio@550000b0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port20x: gpio@550000b8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port21x: gpio@550000c0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port22x: gpio@550000c8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port23x: gpio@550000d0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port24x: gpio@550000d8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port25x: gpio@550000e0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port26x: gpio@550000e8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port27x: gpio@550000f0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port28x: gpio@550000f8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port29x: gpio@55000100 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000100 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port30x: gpio@55000108 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000108 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ /* i2c4 does not exist */
+
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ bus-width = <4>;
+ };
+
+ emmc: sdhc@5a500000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a500000 0x200>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_emmc>;
+ pinctrl-1 = <&pinctrl_emmc_1v8>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ bus-width = <8>;
+ non-removable;
+ };
+
+ sd1: sdhc@5a600000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a600000 0x200>;
+ interrupts = <0 85 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd1>;
+ pinctrl-1 = <&pinctrl_sd1_1v8>;
+ clocks = <&mio_clk 2>;
+ resets = <&mio_rst 2>, <&mio_rst 5>;
+ bus-width = <4>;
+ };
+
+ usb2: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb3: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
+
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ };
+};
+
+&refclk {
+ clock-frequency = <25000000>;
+};
+
+&serial0 {
+ clock-frequency = <73728000>;
+};
+
+&serial1 {
+ clock-frequency = <73728000>;
+};
+
+&serial2 {
+ clock-frequency = <73728000>;
+};
+
+&serial3 {
+ clock-frequency = <73728000>;
+};
+
+&mio_clk {
+ compatible = "socionext,uniphier-pro4-mio-clock";
+};
+
+&mio_rst {
+ compatible = "socionext,uniphier-pro4-mio-reset";
+};
+
+&peri_clk {
+ compatible = "socionext,uniphier-pro4-peri-clock";
+};
+
+&peri_rst {
+ compatible = "socionext,uniphier-pro4-peri-reset";
+};
+
+&pinctrl {
+ compatible = "socionext,uniphier-pro4-pinctrl";
+};
+
+&sys_clk {
+ compatible = "socionext,uniphier-pro4-clock";
+};
+
+&sys_rst {
+ compatible = "socionext,uniphier-pro4-reset";
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-pro5.dtsi"
+
+/ {
+ model = "UniPhier Pro5 4KBOX Board";
+ compatible = "socionext,uniphier-pro5-4kbox", "socionext,uniphier-pro5";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ aliases {
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial1 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier Pro5 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "uniphier-common32.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-pro5";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+};
+
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
+ interrupts = <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
+
+ l3: l3-cache@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port17x: gpio@550000a0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port18x: gpio@550000a8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port19x: gpio@550000b0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port20x: gpio@550000b8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port21x: gpio@550000c0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port22x: gpio@550000c8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port23x: gpio@550000d0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port24x: gpio@550000d8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port25x: gpio@550000e0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port26x: gpio@550000e8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port27x: gpio@550000f0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port28x: gpio@550000f8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port29x: gpio@55000100 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000100 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port30x: gpio@55000108 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000108 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ /* i2c4 does not exist */
+
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ emmc: sdhc@68400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x68400000 0x800>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 6>;
+ bus-width = <8>;
+ non-removable;
+ };
+
+ sd: sdhc@68800000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x68800000 0x800>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host";
+ resets = <&mio_rst 0>;
+ bus-width = <4>;
+ };
+
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
+
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
+ };
+};
+
+&refclk {
+ clock-frequency = <20000000>;
+};
+
+&serial0 {
+ clock-frequency = <73728000>;
+};
+
+&serial1 {
+ clock-frequency = <73728000>;
+};
+
+&serial2 {
+ clock-frequency = <73728000>;
+};
+
+&serial3 {
+ clock-frequency = <73728000>;
+};
+
+&mio_clk {
+ compatible = "socionext,uniphier-pro5-mio-clock";
+};
+
+&mio_rst {
+ compatible = "socionext,uniphier-pro5-mio-reset";
+};
+
+&peri_clk {
+ compatible = "socionext,uniphier-pro5-peri-clock";
+};
+
+&peri_rst {
+ compatible = "socionext,uniphier-pro5-peri-reset";
+};
+
+&pinctrl {
+ compatible = "socionext,uniphier-pro5-pinctrl";
+};
+
+&sys_clk {
+ compatible = "socionext,uniphier-pro5-clock";
+};
+
+&sys_rst {
+ compatible = "socionext,uniphier-pro5-reset";
+};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier ProXstream2 Gentil Board
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "uniphier-proxstream2.dtsi"
-
-/ {
- model = "UniPhier ProXstream2 Gentil Board";
- compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial2;
- serial1 = &serial0;
- serial2 = &serial1;
- i2c0 = &i2c0;
- i2c2 = &i2c2;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- eeprom {
- compatible = "24c64", "i2c-eeprom";
- reg = <0x54>;
- u-boot,i2c-offset-len = <2>;
- };
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial2 {
- u-boot,dm-pre-reloc;
-};
-
-&mio_clk {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier ProXstream2 Vodka Board
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "uniphier-proxstream2.dtsi"
-
-/ {
- model = "UniPhier ProXstream2 Vodka Board";
- compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial2;
- serial1 = &serial0;
- serial2 = &serial1;
- i2c0 = &i2c0;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial2 {
- u-boot,dm-pre-reloc;
-};
-
-&mio_clk {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
- u-boot,dm-pre-reloc;
-};
+++ /dev/null
-/*
- * Device Tree Source for UniPhier ProXstream2 SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,proxstream2";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- next-level-cache = <&l2>;
- };
-
- cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <2>;
- next-level-cache = <&l2>;
- };
-
- cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <3>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
- cache-unified;
- cache-size = <(1280 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port15x: gpio@55000080 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000080 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port17x: gpio@550000a0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port18x: gpio@550000a8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port19x: gpio@550000b0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port20x: gpio@550000b8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port21x: gpio@550000c0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port22x: gpio@550000c8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port23x: gpio@550000d0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port24x: gpio@550000d8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port25x: gpio@550000e0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port26x: gpio@550000e8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port27x: gpio@550000f0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port28x: gpio@550000f8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- /* chip-internal connection for STM */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- emmc: sdhc@5a000000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a000000 0x800>;
- interrupts = <0 78 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_emmc>;
- clocks = <&mio_clk 1>;
- bus-width = <8>;
- non-removable;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio_clk 0>;
- bus-width = <4>;
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- interrupts = <0 134 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
- };
-
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- interrupts = <0 137 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
- };
-};
-
-&refclk {
- clock-frequency = <25000000>;
-};
-
-&serial0 {
- clock-frequency = <88900000>;
-};
-
-&serial1 {
- clock-frequency = <88900000>;
-};
-
-&serial2 {
- clock-frequency = <88900000>;
-};
-
-&serial3 {
- clock-frequency = <88900000>;
-};
-
-&mio_clk {
- compatible = "socionext,uniphier-pxs2-mio-clock";
-};
-
-&mio_rst {
- compatible = "socionext,uniphier-pxs2-mio-reset";
-};
-
-&peri_clk {
- compatible = "socionext,uniphier-pxs2-peri-clock";
-};
-
-&peri_rst {
- compatible = "socionext,uniphier-pxs2-peri-reset";
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-pxs2-pinctrl";
-};
-
-&sys_clk {
- compatible = "socionext,uniphier-pxs2-clock";
-};
-
-&sys_rst {
- compatible = "socionext,uniphier-pxs2-reset";
-};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PXs2 Gentil Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-pxs2.dtsi"
+
+/ {
+ model = "UniPhier PXs2 Gentil Board";
+ compatible = "socionext,uniphier-pxs2-gentil",
+ "socionext,uniphier-pxs2";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial2;
+ serial1 = &serial0;
+ serial2 = &serial1;
+ i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
+ reg = <0x54>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial2 {
+ u-boot,dm-pre-reloc;
+};
+
+&mio_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PXs2 Vodka Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-pxs2.dtsi"
+
+/ {
+ model = "UniPhier PXs2 Vodka Board";
+ compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial2;
+ serial1 = &serial0;
+ serial2 = &serial1;
+ i2c0 = &i2c0;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial2 {
+ u-boot,dm-pre-reloc;
+};
+
+&mio_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PXs2 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "uniphier-common32.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-pxs2";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+};
+
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(1280 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port15x: gpio@55000080 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000080 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port16x: gpio@55000088 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000088 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port17x: gpio@550000a0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port18x: gpio@550000a8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port19x: gpio@550000b0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port20x: gpio@550000b8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port21x: gpio@550000c0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port22x: gpio@550000c8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port23x: gpio@550000d0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port24x: gpio@550000d8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port25x: gpio@550000e0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port26x: gpio@550000e8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port27x: gpio@550000f0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port28x: gpio@550000f8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ interrupts = <0 43 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for DMD */
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ /* chip-internal connection for STM */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ emmc: sdhc@5a000000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a000000 0x800>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 6>;
+ bus-width = <8>;
+ non-removable;
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x800>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host";
+ resets = <&mio_rst 0>;
+ bus-width = <4>;
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+ };
+
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+ };
+};
+
+&refclk {
+ clock-frequency = <25000000>;
+};
+
+&serial0 {
+ clock-frequency = <88900000>;
+};
+
+&serial1 {
+ clock-frequency = <88900000>;
+};
+
+&serial2 {
+ clock-frequency = <88900000>;
+};
+
+&serial3 {
+ clock-frequency = <88900000>;
+};
+
+&mio_clk {
+ compatible = "socionext,uniphier-pxs2-mio-clock";
+};
+
+&mio_rst {
+ compatible = "socionext,uniphier-pxs2-mio-reset";
+};
+
+&peri_clk {
+ compatible = "socionext,uniphier-pxs2-peri-clock";
+};
+
+&peri_rst {
+ compatible = "socionext,uniphier-pxs2-peri-reset";
+};
+
+&pinctrl {
+ compatible = "socionext,uniphier-pxs2-pinctrl";
+};
+
+&sys_clk {
+ compatible = "socionext,uniphier-pxs2-clock";
+};
+
+&sys_rst {
+ compatible = "socionext,uniphier-pxs2-reset";
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier sLD3 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-sld3.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier sLD3 Reference Board";
+ compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000
+ 0xc0000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+};
+
+ðsc {
+ interrupts = <0 49 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier sLD3 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-sld3";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24576000>;
+ };
+
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ iobus_clk: iobus_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+ u-boot,dm-pre-reloc;
+
+ timer@20000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@20000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x20000600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@20001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x20001000 0x1000>,
+ <0x20000100 0x100>;
+ };
+
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(512 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clock-frequency = <36864000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clock-frequency = <36864000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clock-frequency = <36864000>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port16x: gpio@55000088 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000088 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for DMD */
+ i2c4: i2c@58600000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58600000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+ u-boot,dm-pre-reloc;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-sld3-mio-clock";
+ #clock-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-sld3-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ emmc: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_emmc>;
+ pinctrl-1 = <&pinctrl_emmc_1v8>;
+ clocks = <&mio_clk 1>;
+ resets = <&mio_rst 1>, <&mio_rst 4>;
+ bus-width = <8>;
+ non-removable;
+ };
+
+ sd: sdhc@5a500000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a500000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ bus-width = <4>;
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ usb3: usb@5a830100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a830100 0x100>;
+ interrupts = <0 83 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
+ <&mio_rst 15>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-sld3-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@f1830000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0xf1830000 0x200>;
+ };
+
+ sysctrl@f1840000 {
+ compatible = "socionext,uniphier-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0xf1840000 0x4000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-sld3-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-sld3-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ nand: nand@f8000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for UniPhier sLD8 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-sld8.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier sLD8 Reference Board";
+ compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&serial3 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier sLD8 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "uniphier-common32.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-sld8";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ clocks {
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ iobus_clk: iobus_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ };
+};
+
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(256 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port16x: gpio@55000088 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000088 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ bus-width = <4>;
+ };
+
+ emmc: sdhc@5a500000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ interrupts = <0 78 4>;
+ reg = <0x5a500000 0x200>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_emmc>;
+ pinctrl-1 = <&pinctrl_emmc_1v8>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ bus-width = <8>;
+ non-removable;
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ aidet@61830000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x61830000 0x200>;
+ };
+};
+
+&refclk {
+ clock-frequency = <25000000>;
+};
+
+&serial0 {
+ clock-frequency = <80000000>;
+};
+
+&serial1 {
+ clock-frequency = <80000000>;
+};
+
+&serial2 {
+ clock-frequency = <80000000>;
+};
+
+&serial3 {
+ interrupts = <0 29 4>;
+ clock-frequency = <80000000>;
+};
+
+&mio_clk {
+ compatible = "socionext,uniphier-sld8-mio-clock";
+};
+
+&mio_rst {
+ compatible = "socionext,uniphier-sld8-mio-reset";
+};
+
+&peri_clk {
+ compatible = "socionext,uniphier-sld8-peri-clock";
+};
+
+&peri_rst {
+ compatible = "socionext,uniphier-sld8-peri-reset";
+};
+
+&pinctrl {
+ compatible = "socionext,uniphier-sld8-pinctrl";
+};
+
+&sys_clk {
+ compatible = "socionext,uniphier-sld8-clock";
+};
+
+&sys_rst {
+ compatible = "socionext,uniphier-sld8-reset";
+};
static const struct uniphier_board_id uniphier_boards[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- { "socionext,ph1-sld3", &uniphier_sld3_data, },
+ { "socionext,uniphier-sld3", &uniphier_sld3_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
- { "socionext,ph1-ld4", &uniphier_ld4_data, },
+ { "socionext,uniphier-ld4", &uniphier_ld4_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
- { "socionext,ph1-pro4-ace", &uniphier_pro4_2g_data, },
- { "socionext,ph1-pro4-sanji", &uniphier_pro4_2g_data, },
- { "socionext,ph1-pro4", &uniphier_pro4_data, },
+ { "socionext,uniphier-pro4-ace", &uniphier_pro4_2g_data, },
+ { "socionext,uniphier-pro4-sanji", &uniphier_pro4_2g_data, },
+ { "socionext,uniphier-pro4", &uniphier_pro4_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
- { "socionext,ph1-sld8", &uniphier_sld8_data, },
+ { "socionext,uniphier-sld8", &uniphier_sld8_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- { "socionext,ph1-pro5", &uniphier_pro5_data, },
+ { "socionext,uniphier-pro5", &uniphier_pro5_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
- { "socionext,proxstream2", &uniphier_pxs2_data, },
+ { "socionext,uniphier-pxs2", &uniphier_pxs2_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
- { "socionext,ph1-ld6b", &uniphier_ld6b_data, },
+ { "socionext,uniphier-ld6b", &uniphier_ld6b_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- { "socionext,ph1-ld11", &uniphier_ld11_data, },
+ { "socionext,uniphier-ld11", &uniphier_ld11_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- { "socionext,ph1-ld21", &uniphier_ld21_data, },
- { "socionext,ph1-ld20-ref", &uniphier_ld20_ref_data, },
- { "socionext,ph1-ld20", &uniphier_ld20_data, },
+ { "socionext,uniphier-ld21", &uniphier_ld21_data, },
+ { "socionext,uniphier-ld20-ref", &uniphier_ld20_ref_data, },
+ { "socionext,uniphier-ld20", &uniphier_ld20_data, },
#endif
};
CONFIG_ARCH_UNIPHIER_LD11=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
CONFIG_ARCH_UNIPHIER_LD20=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_UNIPHIER_SLD3=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
Compile the source
------------------
-PH1-sLD3 reference board:
+sLD3 reference board:
$ make uniphier_sld3_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-LD4 reference board:
+LD4 reference board:
$ make uniphier_ld4_sld8_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-sLD8 reference board:
+sLD8 reference board:
$ make uniphier_ld4_sld8_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-sld8-ref
-PH1-Pro4 reference board:
+Pro4 reference board:
$ make uniphier_pro4_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-Pro4 Ace board:
+Pro4 Ace board:
$ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-ace
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro4-ace
-PH1-Pro4 Sanji board:
+Pro4 Sanji board:
$ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-sanji
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro4-sanji
-PH1-Pro5 4KBOX Board:
+Pro5 4KBOX Board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro5-4kbox
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro5-4kbox
-ProXstream2 Gentil board:
+PXs2 Gentil board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-proxstream2-gentil
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pxs2-gentil
-ProXstream2 Vodka board:
+PXs2 Vodka board:
$ make uniphier_pxs2_ld6b_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-LD6b reference board:
+LD6b reference board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ld6b-ref
You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
to use your favorite compiler.
projects / oweals / u-boot.git / commitdiff