PLL/clocks configuration offset in FLASH

diff --git a/u-boot/include/configs/ap121.h b/u-boot/include/configs/ap121.h
index 59f4df44e744e5235cb98545ea5933902e3761af..2053fcf560608263f4c01d1f9966dd826ce2823c 100755 (executable)
--- a/u-boot/include/configs/ap121.h
+++ b/u-boot/include/configs/ap121.h
@@ -963,6 +963,16 @@
        #define PLL_IN_FLASH_DATA_BLOCK_OFFSET  0x00030000
        #define PLL_IN_FLASH_DATA_BLOCK_LENGTH  0x00010000
        #define PLL_IN_FLASH_MAGIC_OFFSET               0x0000FFF0      // last 16 bytes
+#elif defined(CONFIG_FOR_DRAGINO_V2)
+       /*
+        * We will store PLL and CLOCK registers
+        * configuration at the end of environment
+        * sector (64 KB, environment uses only half!)
+        */
+       #define PLL_IN_FLASH_MAGIC                              0x504C4C73
+       #define PLL_IN_FLASH_DATA_BLOCK_OFFSET  0x00030000
+       #define PLL_IN_FLASH_DATA_BLOCK_LENGTH  0x00010000
+       #define PLL_IN_FLASH_MAGIC_OFFSET               0x0000FFF0      // last 16 bytes
 #else
        /*
         * All TP-Link routers have a lot of unused space