ARM: UniPhier: add device tree sources
authorMasahiro Yamada <yamada.m@jp.panasonic.com>
Wed, 26 Nov 2014 09:33:59 +0000 (18:33 +0900)
committerMasahiro Yamada <yamada.m@jp.panasonic.com>
Thu, 27 Nov 2014 17:20:56 +0000 (02:20 +0900)
This commit adds basic device tree sources for UniPhier SoCs/boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
arch/arm/dts/Makefile
arch/arm/dts/uniphier-ph1-ld4-ref.dts [new file with mode: 0644]
arch/arm/dts/uniphier-ph1-ld4.dtsi [new file with mode: 0644]
arch/arm/dts/uniphier-ph1-pro4-ref.dts [new file with mode: 0644]
arch/arm/dts/uniphier-ph1-pro4.dtsi [new file with mode: 0644]
arch/arm/dts/uniphier-ph1-sld8-ref.dts [new file with mode: 0644]
arch/arm/dts/uniphier-ph1-sld8.dtsi [new file with mode: 0644]

index e5846eac6fa8e172998d1975c5dec23632a25e8f..01df9a9f0e1f6a567b1410453abe85d3bb022d7b 100644 (file)
@@ -32,6 +32,10 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
        tegra114-dalmore.dtb \
        tegra124-jetson-tk1.dtb \
        tegra124-venice2.dtb
+dtb-$(CONFIG_ARCH_UNIPHIER) += \
+       uniphier-ph1-pro4-ref.dtb \
+       uniphier-ph1-ld4-ref.dtb \
+       uniphier-ph1-sld8-ref.dtb
 dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
        zynq-zc706.dtb \
        zynq-zed.dtb \
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
new file mode 100644 (file)
index 0000000..bc8ead4
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld4.dtsi"
+
+/ {
+       model = "Panasonic UniPhier PH1-LD4 Reference Board";
+       compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x20000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyPS0,115200 earlyprintk";
+       };
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
new file mode 100644 (file)
index 0000000..ee53d9c
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       compatible = "panasonic,ph1-ld4";
+
+       cpus {
+               #size-cells = <0>;
+               #address-cells = <1>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0>;
+               };
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+       };
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
new file mode 100644 (file)
index 0000000..03091a8
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+       model = "Panasonic UniPhier PH1-Pro4 Reference Board";
+       compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x40000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyPS0,115200 earlyprintk";
+       };
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
new file mode 100644 (file)
index 0000000..7619c36
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       compatible = "panasonic,ph1-pro4";
+
+       cpus {
+               #size-cells = <0>;
+               #address-cells = <1>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <1>;
+               };
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+       };
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
new file mode 100644 (file)
index 0000000..e7969af
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld8.dtsi"
+
+/ {
+       model = "Panasonic UniPhier PH1-sLD8 Reference Board";
+       compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x20000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyPS0,115200 earlyprintk";
+       };
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
new file mode 100644 (file)
index 0000000..2f895e9
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       compatible = "panasonic,ph1-sld8";
+
+       cpus {
+               #size-cells = <0>;
+               #address-cells = <1>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0>;
+               };
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+       };
+};