ARM: dts: uniphier: add outer cache nodes

These nodes are not parsed by U-Boot for now, but syncing device trees
with Linux is helpful for easier diffing.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 13d6a74cb2d20b1813be74ad7b6befcd9588e2f9..856c207b13645cac700ae8abff54bf0821d42736 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -19,6 +19,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -44,6 +45,17 @@
 };
 
 &soc {
+       l2: l2-cache@500c0000 {
+               compatible = "socionext,uniphier-system-cache";
+               reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+               interrupts = <0 174 4>, <0 175 4>;
+               cache-unified;
+               cache-size = <(512 * 1024)>;
+               cache-sets = <256>;
+               cache-line-size = <128>;
+               cache-level = <2>;
+       };
+
        i2c0: i2c@58400000 {
                compatible = "socionext,uniphier-i2c";
                status = "disabled";

diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 2880062d27c55b0208446953510d57d72af2fbd9..244ccf67e6637712787f673229e5c5bfabed8f0b 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -20,12 +20,14 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -51,6 +53,17 @@
 };
 
 &soc {
+       l2: l2-cache@500c0000 {
+               compatible = "socionext,uniphier-system-cache";
+               reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+               interrupts = <0 174 4>, <0 175 4>;
+               cache-unified;
+               cache-size = <(768 * 1024)>;
+               cache-sets = <256>;
+               cache-line-size = <128>;
+               cache-level = <2>;
+       };
+
        i2c0: i2c@58780000 {
                compatible = "socionext,uniphier-fi2c";
                status = "disabled";
@@ -140,27 +153,27 @@
                compatible = "socionext,uniphier-ehci", "generic-ehci";
                status = "disabled";
                reg = <0x5a810100 0x100>;
+               interrupts = <0 81 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb3>;
-               interrupts = <0 81 4>;
        };
 
        usb0: usb@65a00000 {
                compatible = "socionext,uniphier-xhci", "generic-xhci";
                status = "disabled";
                reg = <0x65a00000 0x100>;
+               interrupts = <0 134 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb0>;
-               interrupts = <0 134 4>;
        };
 
        usb1: usb@65c00000 {
                compatible = "socionext,uniphier-xhci", "generic-xhci";
                status = "disabled";
                reg = <0x65c00000 0x100>;
+               interrupts = <0 137 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb1>;
-               interrupts = <0 137 4>;
        };
 };
 

diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 876242f81ba22714ef740b2131704a34a8a2ba43..00491062fe74ea99b34530b4e791871128050bbe 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -20,12 +20,14 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -51,6 +53,29 @@
 };
 
 &soc {
+       l2: l2-cache@500c0000 {
+               compatible = "socionext,uniphier-system-cache";
+               reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
+               interrupts = <0 190 4>, <0 191 4>;
+               cache-unified;
+               cache-size = <(2 * 1024 * 1024)>;
+               cache-sets = <512>;
+               cache-line-size = <128>;
+               cache-level = <2>;
+               next-level-cache = <&l3>;
+       };
+
+       l3: l3-cache@500c8000 {
+               compatible = "socionext,uniphier-system-cache";
+               reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
+               interrupts = <0 174 4>, <0 175 4>;
+               cache-unified;
+               cache-size = <(2 * 1024 * 1024)>;
+               cache-sets = <512>;
+               cache-line-size = <256>;
+               cache-level = <3>;
+       };
+
        i2c0: i2c@58780000 {
                compatible = "socionext,uniphier-fi2c";
                status = "disabled";
@@ -131,18 +156,18 @@
                compatible = "socionext,uniphier-xhci", "generic-xhci";
                status = "disabled";
                reg = <0x65a00000 0x100>;
+               interrupts = <0 134 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb0>;
-               interrupts = <0 134 4>;
        };
 
        usb1: usb@65c00000 {
                compatible = "socionext,uniphier-xhci", "generic-xhci";
                status = "disabled";
                reg = <0x65c00000 0x100>;
+               interrupts = <0 137 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
-               interrupts = <0 137 4>;
        };
 };
 

diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index bafe343b78445d69eec110b94e99fa716438efe7..cb28bc4508252ebb5517c9d5416c37ff15467131 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -19,6 +19,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -44,6 +45,17 @@
 };
 
 &soc {
+       l2: l2-cache@500c0000 {
+               compatible = "socionext,uniphier-system-cache";
+               reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+               interrupts = <0 174 4>, <0 175 4>;
+               cache-unified;
+               cache-size = <(256 * 1024)>;
+               cache-sets = <256>;
+               cache-line-size = <128>;
+               cache-level = <2>;
+       };
+
        i2c0: i2c@58400000 {
                compatible = "socionext,uniphier-i2c";
                status = "disabled";

diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index cb7df8d46093f21f7ca3e448ce7f8887ad5dd998..3ba6a4ae51d57b8f0867b3cc2484306d552cf391 100644 (file)
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -20,24 +20,28 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <2>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <3>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -63,6 +67,17 @@
 };
 
 &soc {
+       l2: l2-cache@500c0000 {
+               compatible = "socionext,uniphier-system-cache";
+               reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+               interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+               cache-unified;
+               cache-size = <(1280 * 1024)>;
+               cache-sets = <512>;
+               cache-line-size = <128>;
+               cache-level = <2>;
+       };
+
        i2c0: i2c@58780000 {
                compatible = "socionext,uniphier-fi2c";
                status = "disabled";
@@ -152,18 +167,18 @@
                compatible = "socionext,uniphier-xhci", "generic-xhci";
                status = "disabled";
                reg = <0x65a00000 0x100>;
+               interrupts = <0 134 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
-               interrupts = <0 134 4>;
        };
 
        usb1: usb@65c00000 {
                compatible = "socionext,uniphier-xhci", "generic-xhci";
                status = "disabled";
                reg = <0x65c00000 0x100>;
+               interrupts = <0 137 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
-               interrupts = <0 137 4>;
        };
 };