ARM: AM43xx: Add CPSW support to AM43xx EPOS and GP EVM
authorMugunthan V N <mugunthanvnm@ti.com>
Tue, 18 Feb 2014 12:31:54 +0000 (07:31 -0500)
committerTom Rini <trini@ti.com>
Tue, 4 Mar 2014 14:42:06 +0000 (09:42 -0500)
Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected
to RMII and RGMII phy respectively and enable cpsw in config.

Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
board/ti/am43xx/board.c
board/ti/am43xx/mux.c
include/configs/am43xx_evm.h

index 95fd13751b456ac28f88722372e1efd62786f083..0c9f0ef168c72fc13148ff17a75f4339049e9589 100644 (file)
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
+#include <miiphy.h>
+#include <cpsw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_SPL_BUILD
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -402,3 +408,97 @@ int board_late_init(void)
        return 0;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+       /* Additional controls can be added here */
+       return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+       {
+               .slave_reg_ofs  = 0x208,
+               .sliver_reg_ofs = 0xd80,
+               .phy_addr       = 16,
+       },
+       {
+               .slave_reg_ofs  = 0x308,
+               .sliver_reg_ofs = 0xdc0,
+               .phy_addr       = 1,
+       },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+       .mdio_base              = CPSW_MDIO_BASE,
+       .cpsw_base              = CPSW_BASE,
+       .mdio_div               = 0xff,
+       .channels               = 8,
+       .cpdma_reg_ofs          = 0x800,
+       .slaves                 = 1,
+       .slave_data             = cpsw_slaves,
+       .ale_reg_ofs            = 0xd00,
+       .ale_entries            = 1024,
+       .host_port_reg_ofs      = 0x108,
+       .hw_stats_reg_ofs       = 0x900,
+       .bd_ram_ofs             = 0x2000,
+       .mac_control            = (1 << 5),
+       .control                = cpsw_control,
+       .host_port_num          = 0,
+       .version                = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+       int rv;
+       uint8_t mac_addr[6];
+       uint32_t mac_hi, mac_lo;
+
+       /* try reading mac address from efuse */
+       mac_lo = readl(&cdev->macid0l);
+       mac_hi = readl(&cdev->macid0h);
+       mac_addr[0] = mac_hi & 0xFF;
+       mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+       mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+       mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+       mac_addr[4] = mac_lo & 0xFF;
+       mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+       if (!getenv("ethaddr")) {
+               puts("<ethaddr> not set. Validating first E-fuse MAC\n");
+               if (is_valid_ether_addr(mac_addr))
+                       eth_setenv_enetaddr("ethaddr", mac_addr);
+       }
+
+       mac_lo = readl(&cdev->macid1l);
+       mac_hi = readl(&cdev->macid1h);
+       mac_addr[0] = mac_hi & 0xFF;
+       mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+       mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+       mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+       mac_addr[4] = mac_lo & 0xFF;
+       mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+       if (!getenv("eth1addr")) {
+               if (is_valid_ether_addr(mac_addr))
+                       eth_setenv_enetaddr("eth1addr", mac_addr);
+       }
+
+       if (board_is_eposevm()) {
+               writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+               cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+               cpsw_slaves[0].phy_addr = 16;
+       } else {
+               writel(RGMII_MODE_ENABLE, &cdev->miisel);
+               cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+               cpsw_slaves[0].phy_addr = 0;
+       }
+
+       rv = cpsw_register(&cpsw_data);
+       if (rv < 0)
+               printf("Error %d registering CPSW switch\n", rv);
+
+       return rv;
+}
+#endif
index c330a81c4a278e7047fefe2e08eddc1ef1247f0c..77c53d2e90edc481264dcec44adf6704fb5e3dde 100644 (file)
 #include <asm/arch/mux.h>
 #include "board.h"
 
+static struct module_pin_mux rmii1_pin_mux[] = {
+       {OFFSET(mii1_txen), MODE(1)},                   /* RMII1_TXEN */
+       {OFFSET(mii1_txd1), MODE(1)},                   /* RMII1_TD1 */
+       {OFFSET(mii1_txd0), MODE(1)},                   /* RMII1_TD0 */
+       {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},        /* RMII1_RD1 */
+       {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},        /* RMII1_RD0 */
+       {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},        /* RMII1_RXDV */
+       {OFFSET(mii1_crs), MODE(1) | RXACTIVE},         /* RMII1_CRS_DV */
+       {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},       /* RMII1_RXERR */
+       {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},     /* RMII1_refclk */
+       {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+       {OFFSET(mii1_txen), MODE(2)},                   /* RGMII1_TCTL */
+       {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},        /* RGMII1_RCTL */
+       {OFFSET(mii1_txd3), MODE(2)},                   /* RGMII1_TD3 */
+       {OFFSET(mii1_txd2), MODE(2)},                   /* RGMII1_TD2 */
+       {OFFSET(mii1_txd1), MODE(2)},                   /* RGMII1_TD1 */
+       {OFFSET(mii1_txd0), MODE(2)},                   /* RGMII1_TD0 */
+       {OFFSET(mii1_txclk), MODE(2)},                  /* RGMII1_TCLK */
+       {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},       /* RGMII1_RCLK */
+       {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},        /* RGMII1_RD3 */
+       {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},        /* RGMII1_RD2 */
+       {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},        /* RGMII1_RD1 */
+       {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},        /* RGMII1_RD0 */
+       {-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+       {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+       {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
+       {-1},
+};
+
 static struct module_pin_mux uart0_pin_mux[] = {
        {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
        {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
@@ -57,10 +92,15 @@ void enable_board_pin_mux(void)
 {
        configure_module_pin_mux(mmc0_pin_mux);
        configure_module_pin_mux(i2c0_pin_mux);
+       configure_module_pin_mux(mdio_pin_mux);
 
-       if (board_is_gpevm())
+       if (board_is_gpevm()) {
                configure_module_pin_mux(gpio5_7_pin_mux);
-       configure_module_pin_mux(qspi_pin_mux);
+               configure_module_pin_mux(rgmii1_pin_mux);
+       } else if (board_is_eposevm()) {
+               configure_module_pin_mux(rmii1_pin_mux);
+               configure_module_pin_mux(qspi_pin_mux);
+       }
 }
 
 void enable_i2c0_pin_mux(void)
index c773a1836917727535af3e4ebd3680e64fd6fcf7..aff17ee74e428a38bd50f971a0e36d7b5051434c 100644 (file)
        "run mmcboot;" \
        "run usbboot;"
 
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_SYS_RX_ETH_BUFFER       64
+#define CONFIG_PHY_ADDR                        16
+
 #endif
 #endif /* __CONFIG_AM43XX_EVM_H */