ARM: rmobile: Tidy up SYSC_PWRx define of 3DG on Gen3
authorHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Thu, 23 Mar 2017 01:35:41 +0000 (10:35 +0900)
committerMarek Vasut <marex@denx.de>
Thu, 18 Oct 2018 17:07:46 +0000 (19:07 +0200)
Tidy up unused definition related to power control of 3DG.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
board/renesas/draak/draak.c
board/renesas/salvator-x/salvator-x.c
board/renesas/ulcb/ulcb.c

index 71fd5001c45e4451fb677fe2601e5b7be9770a51..060343dfe4df972b35358af3c171ce08a45b566c 100644 (file)
@@ -44,12 +44,6 @@ int board_early_init_f(void)
        return 0;
 }
 
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define        SYSC_PWRSR2     0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define        SYSC_PWRONCR2   0xE618010C
-
 /* HSUSB block registers */
 #define HSUSB_REG_LPSTS                        0xE6590102
 #define HSUSB_REG_LPSTS_SUSPM_NORMAL   BIT(14)
index 726a236af36a051f956fc8865ca5cc91232ec9cf..a1a15316639e7b2280b54835deb117b4aa59ceac 100644 (file)
@@ -44,12 +44,6 @@ int board_early_init_f(void)
        return 0;
 }
 
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define        SYSC_PWRSR2     0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define        SYSC_PWRONCR2   0xE618010C
-
 /* HSUSB block registers */
 #define HSUSB_REG_LPSTS                        0xE6590102
 #define HSUSB_REG_LPSTS_SUSPM_NORMAL   BIT(14)
index a7ca274f34cb673e1ab67ccedccfdceaca434454..e549a2efac93c388c28702758fa56ea1220abc65 100644 (file)
@@ -44,12 +44,6 @@ int board_early_init_f(void)
        return 0;
 }
 
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define        SYSC_PWRSR2     0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define        SYSC_PWRONCR2   0xE618010C
-
 /* HSUSB block registers */
 #define HSUSB_REG_LPSTS                        0xE6590102
 #define HSUSB_REG_LPSTS_SUSPM_NORMAL   BIT(14)