armv8: fsl-layerscape: identify boot source from PORSR register

PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.

Further, it can be used to select the environment location.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix multiple checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 901ecb943a349fb23d292d1077c68754d589023a..0b6f1e1b474c84f00241e858a4cb95c06194e881 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -31,6 +31,10 @@
 #include <hwconfig.h>
 #include <fsl_qbman.h>
 
+#ifdef CONFIG_TFABOOT
+#include <environment.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct cpu_type cpu_type_list[] = {
@@ -581,7 +585,192 @@ void enable_caches(void)
        icache_enable();
        dcache_enable();
 }
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+#ifdef CONFIG_TFABOOT
+enum boot_src __get_boot_src(u32 porsr1)
+{
+       enum boot_src src = BOOT_SOURCE_RESERVED;
+       u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
+#if !defined(CONFIG_FSL_LSCH3_2)
+       u32 val;
+#endif
+       debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
+
+#if defined(CONFIG_FSL_LSCH3)
+#if defined(CONFIG_FSL_LSCH3_2)
+       switch (rcw_src) {
+       case RCW_SRC_SDHC1_VAL:
+               src = BOOT_SOURCE_SD_MMC;
+       break;
+       case RCW_SRC_SDHC2_VAL:
+               src = BOOT_SOURCE_SD_MMC2;
+       break;
+       case RCW_SRC_I2C1_VAL:
+               src = BOOT_SOURCE_I2C1_EXTENDED;
+       break;
+       case RCW_SRC_FLEXSPI_NAND2K_VAL:
+               src = BOOT_SOURCE_XSPI_NAND;
+       break;
+       case RCW_SRC_FLEXSPI_NAND4K_VAL:
+               src = BOOT_SOURCE_XSPI_NAND;
+       break;
+       case RCW_SRC_RESERVED_1_VAL:
+               src = BOOT_SOURCE_RESERVED;
+       break;
+       case RCW_SRC_FLEXSPI_NOR_24B:
+               src = BOOT_SOURCE_XSPI_NOR;
+       break;
+       default:
+               src = BOOT_SOURCE_RESERVED;
+       }
+#else
+       val = rcw_src & RCW_SRC_TYPE_MASK;
+       if (val == RCW_SRC_NOR_VAL) {
+               val = rcw_src & NOR_TYPE_MASK;
+
+               switch (val) {
+               case NOR_16B_VAL:
+               case NOR_32B_VAL:
+                       src = BOOT_SOURCE_IFC_NOR;
+               break;
+               default:
+                       src = BOOT_SOURCE_RESERVED;
+               }
+       } else {
+               /* RCW SRC Serial Flash */
+               val = rcw_src & RCW_SRC_SERIAL_MASK;
+               switch (val) {
+               case RCW_SRC_QSPI_VAL:
+               /* RCW SRC Serial NOR (QSPI) */
+                       src = BOOT_SOURCE_QSPI_NOR;
+                       break;
+               case RCW_SRC_SD_CARD_VAL:
+               /* RCW SRC SD Card */
+                       src = BOOT_SOURCE_SD_MMC;
+                       break;
+               case RCW_SRC_EMMC_VAL:
+               /* RCW SRC EMMC */
+                       src = BOOT_SOURCE_SD_MMC2;
+                       break;
+               case RCW_SRC_I2C1_VAL:
+               /* RCW SRC I2C1 Extended */
+                       src = BOOT_SOURCE_I2C1_EXTENDED;
+                       break;
+               default:
+                       src = BOOT_SOURCE_RESERVED;
+               }
+       }
+#endif
+#elif defined(CONFIG_FSL_LSCH2)
+       /* RCW SRC NAND */
+       val = rcw_src & RCW_SRC_NAND_MASK;
+       if (val == RCW_SRC_NAND_VAL) {
+               val = rcw_src & NAND_RESERVED_MASK;
+               if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
+                       src = BOOT_SOURCE_IFC_NAND;
+
+       } else {
+               /* RCW SRC NOR */
+               val = rcw_src & RCW_SRC_NOR_MASK;
+               if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
+                       src = BOOT_SOURCE_IFC_NOR;
+               } else {
+                       switch (rcw_src) {
+                       case QSPI_VAL1:
+                       case QSPI_VAL2:
+                               src = BOOT_SOURCE_QSPI_NOR;
+                               break;
+                       case SD_VAL:
+                               src = BOOT_SOURCE_SD_MMC;
+                               break;
+                       default:
+                               src = BOOT_SOURCE_RESERVED;
+                       }
+               }
+       }
 #endif
+       debug("%s: src 0x%x\n", __func__, src);
+       return src;
+}
+
+enum boot_src get_boot_src(void)
+{
+       u32 porsr1;
+
+#if defined(CONFIG_FSL_LSCH3)
+       u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+
+       porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+       porsr1 = in_be32(&gur->porsr1);
+#endif
+       debug("%s: porsr1 0x%x\n", __func__, porsr1);
+
+       return __get_boot_src(porsr1);
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+int mmc_get_env_dev(void)
+{
+       enum boot_src src = get_boot_src();
+       int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+       switch (src) {
+       case BOOT_SOURCE_SD_MMC:
+               dev = 0;
+               break;
+       case BOOT_SOURCE_SD_MMC2:
+               dev = 1;
+               break;
+       default:
+               break;
+       }
+
+       return dev;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+       enum boot_src src = get_boot_src();
+       enum env_location env_loc = ENVL_NOWHERE;
+
+       if (prio)
+               return ENVL_UNKNOWN;
+
+       switch (src) {
+       case BOOT_SOURCE_IFC_NOR:
+               env_loc = ENVL_FLASH;
+               break;
+       case BOOT_SOURCE_QSPI_NOR:
+               /* FALLTHROUGH */
+       case BOOT_SOURCE_XSPI_NOR:
+               env_loc = ENVL_SPI_FLASH;
+               break;
+       case BOOT_SOURCE_IFC_NAND:
+               /* FALLTHROUGH */
+       case BOOT_SOURCE_QSPI_NAND:
+               /* FALLTHROUGH */
+       case BOOT_SOURCE_XSPI_NAND:
+               env_loc = ENVL_NAND;
+               break;
+       case BOOT_SOURCE_SD_MMC:
+               /* FALLTHROUGH */
+       case BOOT_SOURCE_SD_MMC2:
+               env_loc =  ENVL_MMC;
+               break;
+       case BOOT_SOURCE_I2C1_EXTENDED:
+               /* FALLTHROUGH */
+       default:
+               break;
+       }
+
+       return env_loc;
+}
+#endif /* CONFIG_TFABOOT */
 
 u32 initiator_type(u32 cluster, int init_id)
 {

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8c10526a6cfb3386a829c7ddf522295a4a0d9e7a..4d0f16f21c2b04f124e261f7a07c3d5b7e6aa64d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -677,6 +677,26 @@ struct ccsr_gpio {
 #define SCR0_CLIENTPD_MASK             0x00000001
 #define SCR0_USFCFG_MASK               0x00000400
 
+#ifdef CONFIG_TFABOOT
+#define RCW_SRC_MASK                   (0xFF800000)
+#define RCW_SRC_BIT                    23
+
+/* RCW SRC NAND */
+#define RCW_SRC_NAND_MASK              (0x100)
+#define RCW_SRC_NAND_VAL               (0x100)
+#define NAND_RESERVED_MASK             (0xFC)
+#define NAND_RESERVED_1                        (0x0)
+#define NAND_RESERVED_2                        (0x80)
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_MASK               (0x1F0)
+#define NOR_8B_VAL                     (0x10)
+#define NOR_16B_VAL                    (0x20)
+#define SD_VAL                         (0x40)
+#define QSPI_VAL1                      (0x44)
+#define QSPI_VAL2                      (0x45)
+#endif
+
 uint get_svr(void);
 
 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index b0cec74db0ddba6e932b59ce9d18396d6ed6e9fc..8ddff55dac73fb7ec362cd4879d5b2aaaf4366ac 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -82,6 +82,55 @@
 #define CONFIG_SYS_FSL_JR0_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
+#ifdef CONFIG_TFABOOT
+#ifdef CONFIG_FSL_LSCH3_2
+/* RCW_SRC field in Power-On Reset Control Register 1 */
+#define RCW_SRC_MASK                   0x07800000
+#define RCW_SRC_BIT                    23
+
+/* CFG_RCW_SRC[3:0] */
+#define RCW_SRC_TYPE_MASK              0x8
+#define RCW_SRC_ADDR_OFFSET_8MB                0x800000
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL          0x0     /* 0x00 - 0x07 */
+
+#define RCW_SRC_SDHC1_VAL              0x8     /* 0x8 */
+#define RCW_SRC_SDHC2_VAL              0x9     /* 0x9 */
+#define RCW_SRC_I2C1_VAL               0xa     /* 0xa */
+#define RCW_SRC_RESERVED_UART_VAL      0xb     /* 0xb */
+#define RCW_SRC_FLEXSPI_NAND2K_VAL     0xc     /* 0xc */
+#define RCW_SRC_FLEXSPI_NAND4K_VAL     0xd     /* 0xd */
+#define RCW_SRC_RESERVED_1_VAL         0xe     /* 0xe */
+#define RCW_SRC_FLEXSPI_NOR_24B                0xf     /* 0xf */
+#else
+#define RCW_SRC_MASK                   (0xFF800000)
+#define RCW_SRC_BIT                    23
+/* CFG_RCW_SRC[6:0] */
+#define RCW_SRC_TYPE_MASK               (0x70)
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL           (0x10)     /* 0x10 - 0x1f */
+/* Hardcoded will also have CFG_RCW_SRC[7] as 1.   0x90 - 0x9f */
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_VAL                 (0x20)
+#define NOR_TYPE_MASK                   (0x10)
+#define NOR_16B_VAL                     (0x0)       /* 0x20 - 0x2f */
+#define NOR_32B_VAL                     (0x10)       /* 0x30 - 0x3f */
+
+/* RCW SRC Serial Flash
+ * 1. SERIAL NOR (QSPI)
+ * 2. OTHERS (SD/MMC, SPI, I2C1
+ */
+#define RCW_SRC_SERIAL_MASK             (0x7F)
+#define RCW_SRC_QSPI_VAL                (0x62)     /* 0x62 */
+#define RCW_SRC_SD_CARD_VAL             (0x40)     /* 0x40 */
+#define RCW_SRC_EMMC_VAL                (0x41)     /* 0x41 */
+#define RCW_SRC_I2C1_VAL                (0x49)     /* 0x49 */
+#endif
+#endif
+
 /* Security Monitor */
 #define CONFIG_SYS_SEC_MON_ADDR                (CONFIG_SYS_IMMR + 0x00e90000)
 

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 61b6e4bf07ee5b0fb8ad73339fd46c442cb87e57..d327c7ba1f1657b71b6439fe4a803ff824c48da5 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -53,6 +53,23 @@ struct cpu_type {
 
 #define CPU_TYPE_ENTRY(n, v, nc) \
        { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#ifdef CONFIG_TFABOOT
+enum boot_src {
+       BOOT_SOURCE_RESERVED = 0,
+       BOOT_SOURCE_IFC_NOR,
+       BOOT_SOURCE_IFC_NAND,
+       BOOT_SOURCE_QSPI_NOR,
+       BOOT_SOURCE_QSPI_NAND,
+       BOOT_SOURCE_XSPI_NOR,
+       BOOT_SOURCE_XSPI_NAND,
+       BOOT_SOURCE_SD_MMC,
+       BOOT_SOURCE_SD_MMC2,
+       BOOT_SOURCE_I2C1_EXTENDED,
+};
+
+enum boot_src get_boot_src(void);
+#endif
 #endif
 #define SVR_WO_E               0xFFFFFE
 #define SVR_LS1012A            0x870400