F: arch/arm/cpu/armv8/hisilicon
F: arch/arm/include/asm/arch-hi6220/
-ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
+ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX
M: Prafulla Wadaskar <prafulla@marvell.com>
M: Luka Perkov <luka.perkov@sartura.hr>
M: Stefan Roese <sr@denx.de>
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mvebu/
F: drivers/ata/ahci_mvebu.c
+F: drivers/phy/marvell/
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Marvell International Ltd.
- */
-
-#ifndef _COMPHY_H_
-#define _COMPHY_H_
-
-#include <dt-bindings/comphy/comphy_data.h>
-#include <fdtdec.h>
-
-#if defined(DEBUG)
-#define debug_enter() printf("----> Enter %s\n", __func__);
-#define debug_exit() printf("<---- Exit %s\n", __func__);
-#else
-#define debug_enter()
-#define debug_exit()
-#endif
-
-/* COMPHY registers */
-#define COMMON_PHY_CFG1_REG 0x0
-#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
-#define COMMON_PHY_CFG1_PWR_UP_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
-#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
-#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
- (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
-#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
-#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
-#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
-#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
- (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
-#define COMMON_PHY_PHY_MODE_OFFSET 15
-#define COMMON_PHY_PHY_MODE_MASK \
- (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
-
-#define COMMON_PHY_CFG6_REG 0x14
-#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
-#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
- (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
-
-#define COMMON_SELECTOR_PHY_OFFSET 0x140
-#define COMMON_SELECTOR_PIPE_OFFSET 0x144
-
-#define COMMON_PHY_SD_CTRL1 0x148
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
-#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
-#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
-
-/* ToDo: Get this address via DT */
-#define MVEBU_CP0_REGS_BASE 0xF2000000UL
-
-#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
-#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
-#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
- (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
-
-#define MAX_LANE_OPTIONS 10
-#define MAX_UTMI_PHY_COUNT 3
-
-struct comphy_mux_options {
- u32 type;
- u32 mux_value;
-};
-
-struct comphy_mux_data {
- u32 max_lane_values;
- struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
-};
-
-struct comphy_map {
- u32 type;
- u32 speed;
- u32 invert;
- bool clk_src;
- bool end_point;
-};
-
-struct chip_serdes_phy_config {
- struct comphy_mux_data *mux_data;
- int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
- struct comphy_map *);
- void __iomem *comphy_base_addr;
- void __iomem *hpipe3_base_addr;
- u32 comphy_lanes_count;
- u32 comphy_mux_bitcount;
- const fdt32_t *comphy_mux_lane_order;
- u32 cp_index;
-};
-
-/* Register helper functions */
-static inline void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
-{
- u32 reg_data;
-
- reg_data = readl(addr);
- reg_data &= ~mask;
- reg_data |= data;
- writel(reg_data, addr);
-}
-
-static inline void reg_set(void __iomem *addr, u32 data, u32 mask)
-{
- debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
- (unsigned long)addr, data, mask);
- debug("old value = %#010x ==> ", readl(addr));
- reg_set_silent(addr, data, mask);
- debug("new value %#010x\n", readl(addr));
-}
-
-static inline void reg_set_silent16(void __iomem *addr, u16 data, u16 mask)
-{
- u16 reg_data;
-
- reg_data = readw(addr);
- reg_data &= ~mask;
- reg_data |= data;
- writew(reg_data, addr);
-}
-
-static inline void reg_set16(void __iomem *addr, u16 data, u16 mask)
-{
- debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
- (unsigned long)addr, data, mask);
- debug("old value = %#06x ==> ", readw(addr));
- reg_set_silent16(addr, data, mask);
- debug("new value %#06x\n", readw(addr));
-}
-
-/* SoC specific init functions */
-#ifdef CONFIG_ARMADA_3700
-int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map);
-#else
-static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map)
-{
- /*
- * This function should never be called in this configuration, so
- * lets return an error here.
- */
- return -1;
-}
-#endif
-
-#ifdef CONFIG_ARMADA_8K
-int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map);
-#else
-static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map)
-{
- /*
- * This function should never be called in this configuration, so
- * lets return an error here.
- */
- return -1;
-}
-#endif
-
-void comphy_dedicated_phys_init(void);
-
-/* MUX function */
-void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *comphy_map_data,
- void __iomem *selector_base);
-
-void comphy_pcie_config_set(u32 comphy_max_count,
- struct comphy_map *serdes_map);
-void comphy_pcie_config_detect(u32 comphy_max_count,
- struct comphy_map *serdes_map);
-void comphy_pcie_unit_general_config(u32 pex_index);
-
-#endif /* _COMPHY_H_ */
-
#ifndef _COMPHY_A3700_H_
#define _COMPHY_A3700_H_
-#include "comphy.h"
+#include "comphy_core.h"
#include "comphy_hpipe.h"
#define MVEBU_REG(offs) \
#include <linux/errno.h>
#include <asm/io.h>
-#include "comphy.h"
+#include "comphy_core.h"
#define COMPHY_MAX_CHIP 4
}
}
+__weak int comphy_update_map(struct comphy_map *serdes_map, int count)
+{
+ return 0;
+}
+
static int comphy_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
int lane;
int last_idx = 0;
static int current_idx;
+ int res;
/* Save base addresses for later use */
chip_cfg->comphy_base_addr = (void *)devfdt_get_addr_index(dev, 0);
lane++;
}
+ res = comphy_update_map(comphy_map_data, chip_cfg->comphy_lanes_count);
+ if (res < 0)
+ return res;
+
/* Save CP index for MultiCP devices (A8K) */
chip_cfg->cp_index = current_idx++;
/* PHY power UP sequence */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ */
+
+#ifndef _COMPHY_CORE_H_
+#define _COMPHY_CORE_H_
+
+#include <fdtdec.h>
+#include <mvebu/comphy.h>
+
+#if defined(DEBUG)
+#define debug_enter() printf("----> Enter %s\n", __func__);
+#define debug_exit() printf("<---- Exit %s\n", __func__);
+#else
+#define debug_enter()
+#define debug_exit()
+#endif
+
+/* COMPHY registers */
+#define COMMON_PHY_CFG1_REG 0x0
+#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
+#define COMMON_PHY_CFG1_PWR_UP_MASK \
+ (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
+#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
+#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
+ (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
+#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
+#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
+ (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
+#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
+#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
+ (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
+#define COMMON_PHY_PHY_MODE_OFFSET 15
+#define COMMON_PHY_PHY_MODE_MASK \
+ (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
+
+#define COMMON_PHY_CFG6_REG 0x14
+#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
+#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
+ (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
+
+#define COMMON_SELECTOR_PHY_OFFSET 0x140
+#define COMMON_SELECTOR_PIPE_OFFSET 0x144
+
+#define COMMON_PHY_SD_CTRL1 0x148
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
+ (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
+ (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
+#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
+#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
+ (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
+#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
+#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
+ (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
+
+/* ToDo: Get this address via DT */
+#define MVEBU_CP0_REGS_BASE 0xF2000000UL
+
+#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
+#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
+#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
+ (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
+
+#define MAX_LANE_OPTIONS 10
+#define MAX_UTMI_PHY_COUNT 3
+
+struct comphy_mux_options {
+ u32 type;
+ u32 mux_value;
+};
+
+struct comphy_mux_data {
+ u32 max_lane_values;
+ struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
+};
+
+struct chip_serdes_phy_config {
+ struct comphy_mux_data *mux_data;
+ int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
+ struct comphy_map *);
+ void __iomem *comphy_base_addr;
+ void __iomem *hpipe3_base_addr;
+ u32 comphy_lanes_count;
+ u32 comphy_mux_bitcount;
+ const fdt32_t *comphy_mux_lane_order;
+ u32 cp_index;
+};
+
+/* Register helper functions */
+static inline void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
+{
+ u32 reg_data;
+
+ reg_data = readl(addr);
+ reg_data &= ~mask;
+ reg_data |= data;
+ writel(reg_data, addr);
+}
+
+static inline void reg_set(void __iomem *addr, u32 data, u32 mask)
+{
+ debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
+ (unsigned long)addr, data, mask);
+ debug("old value = %#010x ==> ", readl(addr));
+ reg_set_silent(addr, data, mask);
+ debug("new value %#010x\n", readl(addr));
+}
+
+static inline void reg_set_silent16(void __iomem *addr, u16 data, u16 mask)
+{
+ u16 reg_data;
+
+ reg_data = readw(addr);
+ reg_data &= ~mask;
+ reg_data |= data;
+ writew(reg_data, addr);
+}
+
+static inline void reg_set16(void __iomem *addr, u16 data, u16 mask)
+{
+ debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
+ (unsigned long)addr, data, mask);
+ debug("old value = %#06x ==> ", readw(addr));
+ reg_set_silent16(addr, data, mask);
+ debug("new value %#06x\n", readw(addr));
+}
+
+/* SoC specific init functions */
+#ifdef CONFIG_ARMADA_3700
+int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map);
+#else
+static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_ARMADA_8K
+int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map);
+#else
+static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
+#endif
+
+void comphy_dedicated_phys_init(void);
+
+/* MUX function */
+void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *comphy_map_data,
+ void __iomem *selector_base);
+
+void comphy_pcie_config_set(u32 comphy_max_count,
+ struct comphy_map *serdes_map);
+void comphy_pcie_config_detect(u32 comphy_max_count,
+ struct comphy_map *serdes_map);
+void comphy_pcie_unit_general_config(u32 pex_index);
+
+#endif /* _COMPHY_CORE_H_ */
+
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#include "comphy.h"
+#include "comphy_core.h"
#include "comphy_hpipe.h"
#include "sata.h"
#include "utmi_phy.h"
#include <common.h>
#include <asm/io.h>
-#include "comphy.h"
+#include "comphy_core.h"
#include "comphy_hpipe.h"
/*
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ */
+
+#ifndef _MVEBU_COMPHY_H_
+#define _MVEBU_COMPHY_H_
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+struct comphy_map {
+ u32 type;
+ u32 speed;
+ u32 invert;
+ bool clk_src;
+ bool end_point;
+};
+
+int comphy_update_map(struct comphy_map *serdes_map, int count);
+
+#endif /* _MVEBU_COMPHY_H_ */
+
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