// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
- u32 devid, u32 streamid)
+static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
{
u32 *prop;
u32 phandle;
* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
- u32 devid, u32 streamid)
+static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
{
u32 *prop;
u32 iommu_map[4];
}
}
-static void fdt_fixup_pcie(void *blob)
+static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
struct ls_pcie *pcie;
ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
streamid);
/* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
- streamid);
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
+ streamid);
/* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
- streamid);
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
+ streamid);
}
}
#endif
ft_pcie_ls_setup(blob, pcie);
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
- fdt_fixup_pcie(blob);
+ fdt_fixup_pcie_ls(blob);
#endif
}