usb: s3c-otg: Allow custom gusbcfg
authorMarek Vasut <marex@denx.de>
Tue, 4 Nov 2014 03:23:25 +0000 (04:23 +0100)
committerMarek Vasut <marex@denx.de>
Fri, 7 Nov 2014 15:32:02 +0000 (16:32 +0100)
Allow passing in a custom configuration of the gusbcfg register
via platform data.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
drivers/usb/gadget/s3c_udc_otg.c
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
include/usb/s3c_udc.h

index b91005342bee0ad85ce16fb8205c28ca270d3277..7653f03949a114c1d32274a6cd1ff41b32b48c93 100644 (file)
@@ -104,7 +104,7 @@ static void stop_activity(struct s3c_udc *dev,
                          struct usb_gadget_driver *driver);
 static int udc_enable(struct s3c_udc *dev);
 static void udc_set_address(struct s3c_udc *dev, unsigned char address);
-static void reconfig_usbd(void);
+static void reconfig_usbd(struct s3c_udc *dev);
 static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
 static void nuke(struct s3c_ep *ep, int status);
 static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
@@ -215,7 +215,7 @@ static int udc_enable(struct s3c_udc *dev)
        debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
 
        otg_phy_init(dev);
-       reconfig_usbd();
+       reconfig_usbd(dev);
 
        debug_cond(DEBUG_SETUP != 0,
                   "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
@@ -396,15 +396,17 @@ static void stop_activity(struct s3c_udc *dev,
        udc_reinit(dev);
 }
 
-static void reconfig_usbd(void)
+static void reconfig_usbd(struct s3c_udc *dev)
 {
        /* 2. Soft-reset OTG Core and then unreset again. */
        int i;
        unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
+       uint32_t dflt_gusbcfg;
 
        debug("Reseting OTG controller\n");
 
-       writel(0<<15            /* PHY Low Power Clock sel*/
+       dflt_gusbcfg =
+               0<<15           /* PHY Low Power Clock sel*/
                |1<<14          /* Non-Periodic TxFIFO Rewind Enable*/
                |0x5<<10        /* Turnaround time*/
                |0<<9 | 0<<8    /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
@@ -413,8 +415,12 @@ static void reconfig_usbd(void)
                |0<<6           /* 0: high speed utmi+, 1: full speed serial*/
                |0<<4           /* 0: utmi+, 1:ulpi*/
                |1<<3           /* phy i/f  0:8bit, 1:16bit*/
-               |0x7<<0,        /* HS/FS Timeout**/
-               &reg->gusbcfg);
+               |0x7<<0;        /* HS/FS Timeout**/
+
+       if (dev->pdata->usb_gusbcfg)
+               dflt_gusbcfg = dev->pdata->usb_gusbcfg;
+
+       writel(dflt_gusbcfg, &reg->gusbcfg);
 
        /* 3. Put the OTG device core in the disconnected state.*/
        uTemp = readl(&reg->dctl);
index 4f69b22a254ceaa8586955337e90b018943aac63..9c54b462c4ee5bb681832796c11395732df28500 100644 (file)
@@ -551,7 +551,7 @@ static int s3c_udc_irq(int irq, void *_dev)
                                debug_cond(DEBUG_ISR,
                                        "\t\tOTG core got reset (%d)!!\n",
                                        reset_available);
-                               reconfig_usbd();
+                               reconfig_usbd(dev);
                                dev->ep0state = WAIT_FOR_SETUP;
                                reset_available = 0;
                                s3c_udc_pre_setup();
index 70e48f88ee7386e86bba22a71b903f45c11f9359..7f49a4e2d5cfec88c301a69b264d5e8bd1888938 100644 (file)
@@ -108,5 +108,6 @@ struct s3c_plat_otg_data {
        unsigned int    regs_otg;
        unsigned int    usb_phy_ctrl;
        unsigned int    usb_flags;
+       unsigned int    usb_gusbcfg;
 };
 #endif