use correct at91rm9200 register name

This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2.  This
makes code use the register name from chip datasheets.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 1902bd02c5d236e526d0bc2133b2c07dd954e843..98363eb40059db0cc34fa6eed7e8ec309086b810 100644 (file)
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -46,7 +46,7 @@
 #define MC_ASR         0xFFFFFF04
 #define MC_AASR                0xFFFFFF08
 #define EBI_CFGR       0xFFFFFF64
-#define SMC2_CSR       0xFFFFFF70
+#define SMC_CSR0       0xFFFFFF70
 
 /* clocks */
 #define PLLAR          0xFFFFFC28
@@ -146,8 +146,8 @@ SMRDATA:
        .word MC_AASR_VAL
        .word EBI_CFGR
        .word EBI_CFGR_VAL
-       .word SMC2_CSR
-       .word SMC2_CSR_VAL
+       .word SMC_CSR0
+       .word SMC_CSR0_VAL
        .word PLLAR
        .word PLLAR_VAL
        .word PLLBR

diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 5b7212a68f929480e219bee22046754a6dceeb99..951ce160a45f48ff1744123d22b087441cd72fbd 100644 (file)
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -51,7 +51,7 @@
 #define MC_ASR_VAL     0x00000000
 #define MC_AASR_VAL    0x00000000
 #define EBI_CFGR_VAL   0x00000000
-#define SMC2_CSR_VAL   0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL   0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL      0x20263E04 /* 179.712000 MHz for PCK */

diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index d22d350579906ba942ef220673382cccfe3a1f5c..bce5fcd82f520d0993e69f00d0d0702c667fe139 100644 (file)
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -50,7 +50,7 @@
 #define MC_ASR_VAL     0x00000000
 #define MC_AASR_VAL    0x00000000
 #define EBI_CFGR_VAL   0x00000000
-#define SMC2_CSR_VAL   0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL   0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL      0x2026BE04 /* 179,712 MHz for PCK */

diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index f93c3bcd6f31c60f209cbe2551aefc05077b1cef..e9c6d8e7aec97682d2da00eac9b328d8f43de3a8 100644 (file)
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -51,7 +51,7 @@
 #define MC_ASR_VAL     0x00000000
 #define MC_AASR_VAL    0x00000000
 #define EBI_CFGR_VAL   0x00000000
-#define SMC2_CSR_VAL   0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL   0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL      0x2031BE01 /* 184.320000 MHz for PCK */

diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 294221f941657ae14e4c2825dd2933f6bc2cc6fc..2eb4af1554d37278e36cf27c49d256ce562ef9d8 100644 (file)
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -55,7 +55,7 @@
 #define MC_ASR_VAL     0x00000000
 #define MC_AASR_VAL    0x00000000
 #define EBI_CFGR_VAL   0x00000000
-#define SMC2_CSR_VAL   0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL   0x00003084 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL      0x20263E04 /* 180 MHz for PCK */