arm: Remove rd6281a board
authorSimon Glass <sjg@chromium.org>
Mon, 31 Aug 2015 01:19:26 +0000 (19:19 -0600)
committerTom Rini <trini@konsulko.com>
Fri, 11 Sep 2015 18:59:16 +0000 (14:59 -0400)
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/mach-kirkwood/Kconfig
board/Marvell/rd6281a/Kconfig [deleted file]
board/Marvell/rd6281a/MAINTAINERS [deleted file]
board/Marvell/rd6281a/Makefile [deleted file]
board/Marvell/rd6281a/kwbimage.cfg [deleted file]
board/Marvell/rd6281a/rd6281a.c [deleted file]
board/Marvell/rd6281a/rd6281a.h [deleted file]
configs/rd6281a_defconfig [deleted file]
include/configs/rd6281a.h [deleted file]

index 6228f5bc117143243616689f68add1cd494d1422..3002c04098b876a68b26d60f3bca82ef5800ea19 100644 (file)
@@ -4,9 +4,6 @@ choice
        prompt "Marvell Kirkwood board select"
        optional
 
-config TARGET_RD6281A
-       bool "RD6281A Board"
-
 config TARGET_DREAMPLUG
        bool "DreamPlug Board"
 
@@ -60,7 +57,6 @@ endchoice
 config SYS_SOC
        default "kirkwood"
 
-source "board/Marvell/rd6281a/Kconfig"
 source "board/Marvell/dreamplug/Kconfig"
 source "board/Marvell/guruplug/Kconfig"
 source "board/Marvell/sheevaplug/Kconfig"
diff --git a/board/Marvell/rd6281a/Kconfig b/board/Marvell/rd6281a/Kconfig
deleted file mode 100644 (file)
index 025ee26..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_RD6281A
-
-config SYS_BOARD
-       default "rd6281a"
-
-config SYS_VENDOR
-       default "Marvell"
-
-config SYS_CONFIG_NAME
-       default "rd6281a"
-
-endif
diff --git a/board/Marvell/rd6281a/MAINTAINERS b/board/Marvell/rd6281a/MAINTAINERS
deleted file mode 100644 (file)
index d4ad592..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-RD6281A BOARD
-M:     Prafulla Wadaskar <prafulla@marvell.com>
-S:     Maintained
-F:     board/Marvell/rd6281a/
-F:     include/configs/rd6281a.h
-F:     configs/rd6281a_defconfig
diff --git a/board/Marvell/rd6281a/Makefile b/board/Marvell/rd6281a/Makefile
deleted file mode 100644 (file)
index cb77370..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := rd6281a.o
diff --git a/board/Marvell/rd6281a/kwbimage.cfg b/board/Marvell/rd6281a/kwbimage.cfg
deleted file mode 100644 (file)
index f969d92..0000000
+++ /dev/null
@@ -1,151 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM      nand
-NAND_ECC_MODE  default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30     # DDR Configuration register
-# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000     # DDR Controller Control Low
-# bit 4:    0=addr/cmd in smame cycle
-# bit 5:    0=clk is driven during self refresh, we don't care for APX
-# bit 6:    0=use recommended falling edge of clk for addr/cmd
-# bit14:    0=input buffer always powered up
-# bit18:    1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31:    0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451     # DDR Timing (Low) (active cycles value +1)
-# bit3-0:   TRAS lsbs
-# bit7-4:   TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20:    TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33     #  DDR Timing (High)
-# bit6-0:   TRFC
-# bit8-7:   TR2R
-# bit10-9:  TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x00000099     #  DDR Address Control
-# bit1-0:   00, Cs0width=x8
-# bit3-2:   11, Cs0size=1Gb
-# bit5-4:   00, Cs1width=x8
-# bit7-6:   11, Cs1size=1Gb
-# bit9-8:   00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16:    0,  Cs0AddrSel
-# bit17:    0,  Cs1AddrSel
-# bit18:    0,  Cs2AddrSel
-# bit19:    0,  Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000     #  DDR Open Pages Control
-# bit0:    0,  OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000     #  DDR Operation
-# bit3-0:   0x0, DDR cmd
-# bit31-4:  0 required
-
-DATA 0xFFD0141C 0x00000C52     #  DDR Mode
-# bit2-0:   2, BurstLen=2 required
-# bit3:     0, BurstType=0 required
-# bit6-4:   4, CL=5
-# bit7:     0, TestMode=0 normal
-# bit8:     0, DLL reset=0 normal
-# bit11-9:  6, auto-precharge write recovery ????????????
-# bit12:    0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004     #  DDR Extended Mode
-# bit0:    0,  DDR DLL enabled
-# bit1:    0,  DDR drive strenght normal
-# bit2:    1,  DDR ODT control lsd (disabled)
-# bit5-3:  000, required
-# bit6:    0,  DDR ODT control msb, (disabled)
-# bit9-7:  000, required
-# bit10:   0,  differential DQS enabled
-# bit11:   0, required
-# bit12:   0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F     #  DDR Controller Control High
-# bit2-0:  111, required
-# bit3  :  1  , MBUS Burst Chop disabled
-# bit6-4:  111, required
-# bit7  :  0
-# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9  :  0  , no half clock cycle addition to dataout
-# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0    required
-
-DATA 0xFFD01428 0x00085520     # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552     # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000     # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1     # CS[0]n Size
-# bit0:    1,  Window enabled
-# bit1:    0,  Write Protect disabled
-# bit3-2:  00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000     # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5     # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000     # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000     # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00120012     #  DDR ODT Control (Low)
-# bit3-0:  2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
-# bit7-4:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
-# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000     #  DDR ODT Control (High)
-# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
-# bit3-2:  01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F     # CPU ODT Control
-DATA 0xFFD01480 0x00000001     # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
deleted file mode 100644 (file)
index b0020c9..0000000
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "rd6281a.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-       /*
-        * default gpio configuration
-        * There are maximum 64 gpios controlled through 2 sets of registers
-        * the  below configuration configures mainly initial LED status
-        */
-       mvebu_config_gpio(RD6281A_OE_VAL_LOW,
-                         RD6281A_OE_VAL_HIGH,
-                         RD6281A_OE_LOW, RD6281A_OE_HIGH);
-
-       /* Multi-Purpose Pins Functionality configuration */
-       static const u32 kwmpp_config[] = {
-               MPP0_NF_IO2,
-               MPP1_NF_IO3,
-               MPP2_NF_IO4,
-               MPP3_NF_IO5,
-               MPP4_NF_IO6,
-               MPP5_NF_IO7,
-               MPP6_SYSRST_OUTn,
-               MPP7_GPO,
-               MPP8_TW_SDA,
-               MPP9_TW_SCK,
-               MPP10_UART0_TXD,
-               MPP11_UART0_RXD,
-               MPP12_SD_CLK,
-               MPP13_SD_CMD,
-               MPP14_SD_D0,
-               MPP15_SD_D1,
-               MPP16_SD_D2,
-               MPP17_SD_D3,
-               MPP18_NF_IO0,
-               MPP19_NF_IO1,
-               MPP20_GE1_0,
-               MPP21_GE1_1,
-               MPP22_GE1_2,
-               MPP23_GE1_3,
-               MPP24_GE1_4,
-               MPP25_GE1_5,
-               MPP26_GE1_6,
-               MPP27_GE1_7,
-               MPP28_GPIO,
-               MPP29_GPIO,
-               MPP30_GE1_10,
-               MPP31_GE1_11,
-               MPP32_GE1_12,
-               MPP33_GE1_13,
-               MPP34_GE1_14,
-               MPP35_GPIO,
-               MPP36_AUDIO_SPDIFI,
-               MPP37_AUDIO_SPDIFO,
-               MPP38_GPIO,
-               MPP39_TDM_SPI_CS0,
-               MPP40_TDM_SPI_SCK,
-               MPP41_TDM_SPI_MISO,
-               MPP42_TDM_SPI_MOSI,
-               MPP43_TDM_CODEC_INTn,
-               MPP44_GPIO,
-               MPP45_TDM_PCLK,
-               MPP46_TDM_FS,
-               MPP47_TDM_DRX,
-               MPP48_TDM_DTX,
-               MPP49_GPIO,
-               0
-       };
-       kirkwood_mpp_conf(kwmpp_config, NULL);
-       return 0;
-}
-
-int board_init(void)
-{
-       /*
-        * arch number of board
-        */
-       gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
-
-       /* adress of boot parameters */
-       gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
-       return 0;
-}
-
-void mv_phy_88e1116_init(char *name)
-{
-       u16 reg;
-       u16 devadr;
-
-       if (miiphy_set_current_dev(name))
-               return;
-
-       /* command to read PHY dev address */
-       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
-               printf("Err..%s could not read PHY dev address\n",
-                       __FUNCTION__);
-               return;
-       }
-
-       /*
-        * Enable RGMII delay on Tx and Rx for CPU port
-        * Ref: sec 4.7.2 of chip datasheet
-        */
-       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
-       miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
-       reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
-       miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
-       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
-       /* reset the phy */
-       if (miiphy_read (name, devadr, MII_BMCR, &reg) != 0) {
-               printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
-               return;
-       }
-       if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
-               printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
-               return;
-       }
-
-       printf("88E1116 Initialized on %s\n", name);
-}
-
-/* Configure and enable Switch and PHY */
-void reset_phy(void)
-{
-       /* configure and initialize switch */
-       struct mv88e61xx_config swcfg = {
-               .name = "egiga0",
-               .vlancfg = MV88E61XX_VLANCFG_ROUTER,
-               .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
-               .led_init = MV88E61XX_LED_INIT_EN,
-               .portstate = MV88E61XX_PORTSTT_FORWARDING,
-               .cpuport = (1 << 5),
-               .ports_enabled = 0x3f,
-       };
-
-       mv88e61xx_switch_initialize(&swcfg);
-
-       /* configure and initialize PHY */
-       mv_phy_88e1116_init("egiga1");
-}
diff --git a/board/Marvell/rd6281a/rd6281a.h b/board/Marvell/rd6281a/rd6281a.h
deleted file mode 100644 (file)
index 5e1f6a8..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __RD6281A_H
-#define __RD6281A_H
-
-#define RD6281A_OE_LOW                 (~(1 << 7))
-#define RD6281A_OE_HIGH                        (~(1 << 2 | 1 << 12))
-#define RD6281A_OE_VAL_LOW             (0)
-#define RD6281A_OE_VAL_HIGH            (1 << 12)
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG                10
-#define MV88E1116_CPRSP_CR3_REG                21
-#define MV88E1116_MAC_CTRL_REG         21
-#define MV88E1116_PGADR_REG            22
-#define MV88E1116_RGMII_TXTM_CTRL      (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL      (1 << 5)
-
-#endif /* __RD6281A_H */
diff --git a/configs/rd6281a_defconfig b/configs/rd6281a_defconfig
deleted file mode 100644 (file)
index 8fe8594..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_RD6281A=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
deleted file mode 100644 (file)
index a0120b0..0000000
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef _CONFIG_RD6281A_H
-#define _CONFIG_RD6281A_H
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING    "\nMarvell-RD6281A"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131        1       /* CPU Core subversion */
-#define CONFIG_KW88F6281       1       /* SOC Name */
-#define CONFIG_MACH_RD6281A            /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH            /* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_IDE
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND          1
-#define CONFIG_ENV_SECT_SIZE           0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE          1       /* if env in SDRAM */
-#endif
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE                        0x20000 /* 128k */
-#define CONFIG_ENV_ADDR                        0x40000
-#define CONFIG_ENV_OFFSET              0x40000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND             "${x_bootcmd_kernel}; " \
-       "setenv bootargs ${x_bootargs} ${x_bootargs_root}; "    \
-       "${x_bootcmd_usb}; bootm 0x6400000;"
-
-#define CONFIG_MTDPARTS                "orion_nand:512k(uboot),"       \
-       "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS      "x_bootargs=console"    \
-       "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS        \
-       "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
-       "x_bootcmd_usb=usb start\0" \
-       "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS     {1, 1}  /* enable both ports */
-#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
-#define CONFIG_PHY_SPEED       _1000BASET      /*Force PHYspeed to 1GBPs */
-#define CONFIG_PHY_BASE_ADR    0x0A
-#define CONFIG_MV88E61XX_SWITCH        /* Enable MV88E61XX switch driver */
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET     MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET     MV_SATA_PORT1_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#endif /* _CONFIG_RD6281A_H */