/* MDIO module input frequency */
#ifdef CONFIG_SOC_K2G
-#define EMAC_MDIO_BUS_FREQ (clk_get_rate(sys_clk0_3_clk))
+#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk))
#else
-#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk))
#endif
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
return ret;
}
-unsigned long clk_get_rate(unsigned int clk)
+unsigned long ks_clk_get_rate(unsigned int clk)
{
unsigned long freq = 0;
freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
break;
case sys_clk0_2_clk:
- freq = clk_get_rate(sys_clk0_clk) / 2;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 2;
break;
case sys_clk0_3_clk:
- freq = clk_get_rate(sys_clk0_clk) / 3;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 3;
break;
case sys_clk0_4_clk:
- freq = clk_get_rate(sys_clk0_clk) / 4;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 4;
break;
case sys_clk0_6_clk:
- freq = clk_get_rate(sys_clk0_clk) / 6;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 6;
break;
case sys_clk0_8_clk:
- freq = clk_get_rate(sys_clk0_clk) / 8;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 8;
break;
case sys_clk0_12_clk:
- freq = clk_get_rate(sys_clk0_clk) / 12;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 12;
break;
case sys_clk0_24_clk:
- freq = clk_get_rate(sys_clk0_clk) / 24;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 24;
break;
case sys_clk1_3_clk:
- freq = clk_get_rate(sys_clk1_clk) / 3;
+ freq = ks_clk_get_rate(sys_clk1_clk) / 3;
break;
case sys_clk1_4_clk:
- freq = clk_get_rate(sys_clk1_clk) / 4;
+ freq = ks_clk_get_rate(sys_clk1_clk) / 4;
break;
case sys_clk1_6_clk:
- freq = clk_get_rate(sys_clk1_clk) / 6;
+ freq = ks_clk_get_rate(sys_clk1_clk) / 6;
break;
case sys_clk1_12_clk:
- freq = clk_get_rate(sys_clk1_clk) / 12;
+ freq = ks_clk_get_rate(sys_clk1_clk) / 12;
break;
default:
break;
clk = simple_strtoul(argv[1], NULL, 10);
- freq = clk_get_rate(clk);
+ freq = ks_clk_get_rate(clk);
if (freq)
printf("clock index [%d] - frequency %lu\n", clk, freq);
else
void init_plls(void);
void init_pll(const struct pll_init_data *data);
struct pll_init_data *get_pll_init_data(int pll);
-unsigned long clk_get_rate(unsigned int clk);
+unsigned long ks_clk_get_rate(unsigned int clk);
int get_max_dev_speed(int *spds);
int get_max_arm_speed(int *spds);
void pll_pa_clk_sel(void);
#define CONFIG_CONS_INDEX 1
#ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
#else
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2
+#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2
#endif
/* SPI Configuration */
#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_SPI0
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk]
#endif