ARM: keystone: rename clk_get_rate() to ks_clk_get_rate()
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Mon, 26 Sep 2016 11:45:26 +0000 (20:45 +0900)
committerTom Rini <trini@konsulko.com>
Sat, 8 Oct 2016 13:33:13 +0000 (09:33 -0400)
The KeyStone platform has its own clk_get_rate() but its prototype
is different from that of the common-clk (clk-uclass) framework.

Prefix the KeyStone specific implementation with ks_ in order to
avoid name-space conflict.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/include/asm/ti-common/keystone_net.h
arch/arm/mach-keystone/clock.c
arch/arm/mach-keystone/cmd_clock.c
arch/arm/mach-keystone/include/mach/clock.h
include/configs/ti_armv7_keystone2.h

index a0d0d9bd3d79e13fef98b1999961e4e38f97113d..0627728eea84e16fb7a2ee32e2ec23d87abe79c4 100644 (file)
@@ -51,9 +51,9 @@
 
 /* MDIO module input frequency */
 #ifdef CONFIG_SOC_K2G
-#define EMAC_MDIO_BUS_FREQ             (clk_get_rate(sys_clk0_3_clk))
+#define EMAC_MDIO_BUS_FREQ             (ks_clk_get_rate(sys_clk0_3_clk))
 #else
-#define EMAC_MDIO_BUS_FREQ             (clk_get_rate(pass_pll_clk))
+#define EMAC_MDIO_BUS_FREQ             (ks_clk_get_rate(pass_pll_clk))
 #endif
 /* MDIO clock output frequency */
 #define EMAC_MDIO_CLOCK_FREQ           2500000 /* 2.5 MHz */
index b25db1e3fedefc1cce20fec1aa9eec75435bbdc1..d88047242152e25feaeb3d6cc5886ef69823eb81 100644 (file)
@@ -341,7 +341,7 @@ static unsigned long pll_freq_get(int pll)
        return ret;
 }
 
-unsigned long clk_get_rate(unsigned int clk)
+unsigned long ks_clk_get_rate(unsigned int clk)
 {
        unsigned long freq = 0;
 
@@ -381,37 +381,37 @@ unsigned long clk_get_rate(unsigned int clk)
                freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
                break;
        case sys_clk0_2_clk:
-               freq = clk_get_rate(sys_clk0_clk) / 2;
+               freq = ks_clk_get_rate(sys_clk0_clk) / 2;
                break;
        case sys_clk0_3_clk:
-               freq = clk_get_rate(sys_clk0_clk) / 3;
+               freq = ks_clk_get_rate(sys_clk0_clk) / 3;
                break;
        case sys_clk0_4_clk:
-               freq = clk_get_rate(sys_clk0_clk) / 4;
+               freq = ks_clk_get_rate(sys_clk0_clk) / 4;
                break;
        case sys_clk0_6_clk:
-               freq = clk_get_rate(sys_clk0_clk) / 6;
+               freq = ks_clk_get_rate(sys_clk0_clk) / 6;
                break;
        case sys_clk0_8_clk:
-               freq = clk_get_rate(sys_clk0_clk) / 8;
+               freq = ks_clk_get_rate(sys_clk0_clk) / 8;
                break;
        case sys_clk0_12_clk:
-               freq = clk_get_rate(sys_clk0_clk) / 12;
+               freq = ks_clk_get_rate(sys_clk0_clk) / 12;
                break;
        case sys_clk0_24_clk:
-               freq = clk_get_rate(sys_clk0_clk) / 24;
+               freq = ks_clk_get_rate(sys_clk0_clk) / 24;
                break;
        case sys_clk1_3_clk:
-               freq = clk_get_rate(sys_clk1_clk) / 3;
+               freq = ks_clk_get_rate(sys_clk1_clk) / 3;
                break;
        case sys_clk1_4_clk:
-               freq = clk_get_rate(sys_clk1_clk) / 4;
+               freq = ks_clk_get_rate(sys_clk1_clk) / 4;
                break;
        case sys_clk1_6_clk:
-               freq = clk_get_rate(sys_clk1_clk) / 6;
+               freq = ks_clk_get_rate(sys_clk1_clk) / 6;
                break;
        case sys_clk1_12_clk:
-               freq = clk_get_rate(sys_clk1_clk) / 12;
+               freq = ks_clk_get_rate(sys_clk1_clk) / 12;
                break;
        default:
                break;
index 3d5cf3f7f01d5fc2e083715b41db823f971d975e..06afa72519adf7a057190460ed838b8b4911cef1 100644 (file)
@@ -74,7 +74,7 @@ int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
        clk = simple_strtoul(argv[1], NULL, 10);
 
-       freq = clk_get_rate(clk);
+       freq = ks_clk_get_rate(clk);
        if (freq)
                printf("clock index [%d] - frequency %lu\n", clk, freq);
        else
index e2bdec12b8be1174bf3fc3df0b01eb3509b14f66..0d8a9444ded9f6cfa5e6d204930893d1a99b0151 100644 (file)
@@ -125,7 +125,7 @@ extern int speeds[];
 void init_plls(void);
 void init_pll(const struct pll_init_data *data);
 struct pll_init_data *get_pll_init_data(int pll);
-unsigned long clk_get_rate(unsigned int clk);
+unsigned long ks_clk_get_rate(unsigned int clk);
 int get_max_dev_speed(int *spds);
 int get_max_arm_speed(int *spds);
 void pll_pa_clk_sel(void);
index c42dedbbd1951b749fc38b82231f607a4f060829..df265281a35d4f316f8a5017c9d695b1da6c356e 100644 (file)
 #define CONFIG_CONS_INDEX              1
 
 #ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_NS16550_CLK         clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_NS16550_CLK         ks_clk_get_rate(KS2_CLK1_6)
 #else
-#define CONFIG_SYS_NS16550_CLK         clk_get_rate(uart_pll_clk) / 2
+#define CONFIG_SYS_NS16550_CLK         ks_clk_get_rate(uart_pll_clk) / 2
 #endif
 
 /* SPI Configuration */
 #define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI_CLK             clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_SPI_CLK             ks_clk_get_rate(KS2_CLK1_6)
 #define CONFIG_SF_DEFAULT_SPEED                30000000
 #define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
 #define CONFIG_SYS_SPI0
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
 #ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_HZ_CLOCK            clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_HZ_CLOCK            ks_clk_get_rate(KS2_CLK1_6)
 #else
 #define CONFIG_SYS_HZ_CLOCK            external_clk[sys_clk]
 #endif