MIPS: add support for Broadcom MIPS BCM6368 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi
new file mode 100644 (file)
index 0000000..1bb538a
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6368.dtsi
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6368-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6368-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "brcm,bcm6368";
+
+       aliases {
+               spi0 = &spi;
+       };
+
+       cpus {
+               reg = <0x10000000 0x4>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               u-boot,dm-pre-reloc;
+
+               cpu@0 {
+                       compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <0>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               cpu@1 {
+                       compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <1>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               periph_osc: periph-osc {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <50000000>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               periph_clk: periph-clk {
+                       compatible = "brcm,bcm6345-clk";
+                       reg = <0x10000004 0x4>;
+                       #clock-cells = <1>;
+               };
+       };
+
+       pflash: nor@18000000 {
+               compatible = "cfi-flash";
+               reg = <0x18000000 0x2000000>;
+               bank-width = <2>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               status = "disabled";
+       };
+
+       ubus {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               pll_cntl: syscon@10000008 {
+                       compatible = "syscon";
+                       reg = <0x10000008 0x4>;
+               };
+
+               syscon-reboot {
+                       compatible = "syscon-reboot";
+                       regmap = <&pll_cntl>;
+                       offset = <0x0>;
+                       mask = <0x1>;
+               };
+
+               periph_rst: reset-controller@10000010 {
+                       compatible = "brcm,bcm6345-reset";
+                       reg = <0x10000010 0x4>;
+                       #reset-cells = <1>;
+               };
+
+               wdt: watchdog@1000005c {
+                       compatible = "brcm,bcm6345-wdt";
+                       reg = <0x1000005c 0xc>;
+                       clocks = <&periph_osc>;
+               };
+
+               wdt-reboot {
+                       compatible = "wdt-reboot";
+                       wdt = <&wdt>;
+               };
+
+               gpio1: gpio-controller@10000080 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x10000080 0x4>, <0x10000088 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       ngpios = <6>;
+
+                       status = "disabled";
+               };
+
+               gpio0: gpio-controller@10000084 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x10000084 0x4>, <0x1000008c 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               leds: led-controller@100000d0 {
+                       compatible = "brcm,bcm6358-leds";
+                       reg = <0x100000d0 0x8>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               uart0: serial@10000100 {
+                       compatible = "brcm,bcm6345-uart";
+                       reg = <0x10000100 0x18>;
+                       clocks = <&periph_osc>;
+
+                       status = "disabled";
+               };
+
+               uart1: serial@10000120 {
+                       compatible = "brcm,bcm6345-uart";
+                       reg = <0x10000120 0x18>;
+                       clocks = <&periph_osc>;
+
+                       status = "disabled";
+               };
+
+               spi: spi@10000800 {
+                       compatible = "brcm,bcm6358-spi";
+                       reg = <0x10000800 0x70c>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&periph_clk BCM6368_CLK_SPI>;
+                       resets = <&periph_rst BCM6368_RST_SPI>;
+                       spi-max-frequency = <20000000>;
+                       num-cs = <6>;
+
+                       status = "disabled";
+               };
+
+               memory-controller@10001200 {
+                       compatible = "brcm,bcm6358-mc";
+                       reg = <0x10001200 0x4c>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+};

diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index db8b40523af80cfb7eed73d54a888b71fde883eb..4438c62bae32b34ddb1f8315edfbbbd5f6035bd0 100644 (file)
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -10,6 +10,7 @@ config SYS_SOC
        default "bcm6338" if SOC_BMIPS_BCM6338
        default "bcm6348" if SOC_BMIPS_BCM6348
        default "bcm6358" if SOC_BMIPS_BCM6358
+       default "bcm6368" if SOC_BMIPS_BCM6368
        default "bcm63268" if SOC_BMIPS_BCM63268
 
 choice
@@ -70,6 +71,17 @@ config SOC_BMIPS_BCM6358
        help
          This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
 
+config SOC_BMIPS_BCM6368
+       bool "BMIPS BCM6368 family"
+       select SUPPORTS_BIG_ENDIAN
+       select SUPPORTS_CPU_MIPS32_R1
+       select MIPS_TUNE_4KC
+       select MIPS_L1_CACHE_SHIFT_4
+       select SWAP_IO_SPACE
+       select SYSRESET_SYSCON
+       help
+         This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
+
 config SOC_BMIPS_BCM63268
        bool "BMIPS BCM63268 family"
        select SUPPORTS_BIG_ENDIAN

diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
new file mode 100644 (file)
index 0000000..ce35fae
--- /dev/null
+++ b/include/configs/bmips_bcm6368.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6368_H
+#define __CONFIG_BMIPS_BCM6368_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ     200000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET      0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE                  0xb8000000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT      1
+
+#endif /* __CONFIG_BMIPS_BCM6368_H */

diff --git a/include/dt-bindings/clock/bcm6368-clock.h b/include/dt-bindings/clock/bcm6368-clock.h
new file mode 100644 (file)
index 0000000..9d41c0f
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6368-clock.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
+#define __DT_BINDINGS_CLOCK_BCM6368_H
+
+#define BCM6368_CLK_VDSL_QPROC         2
+#define BCM6368_CLK_VDSL_AFE           3
+#define BCM6368_CLK_VDSL_BONDING       4
+#define BCM6368_CLK_VDSL               5
+#define BCM6368_CLK_PHYMIPS            6
+#define BCM6368_CLK_SWPKT_USB          7
+#define BCM6368_CLK_SWPKT_SAR          8
+#define BCM6368_CLK_SPI                        9
+#define BCM6368_CLK_USBD               10
+#define BCM6368_CLK_SAR                        11
+#define BCM6368_CLK_ROBOSW             12
+#define BCM6368_CLK_UTOPIA             13
+#define BCM6368_CLK_PCM                        14
+#define BCM6368_CLK_USBH               15
+#define BCM6368_CLK_GLESS              16
+#define BCM6368_CLK_NAND               17
+#define BCM6368_CLK_IPSEC              18
+#define BCM6368_CLK_USBH_IDDQ          19
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */

diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h
new file mode 100644 (file)
index 0000000..afa6a81
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6368-reset.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6368_H
+#define __DT_BINDINGS_RESET_BCM6368_H
+
+#define BCM6368_RST_SPI                0
+#define BCM6368_RST_MPI                3
+#define BCM6368_RST_IPSEC      4
+#define BCM6368_RST_EPHY       6
+#define BCM6368_RST_SAR                7
+#define BCM6368_RST_SWITCH     10
+#define BCM6368_RST_USBD       11
+#define BCM6368_RST_USBH       12
+#define BCM6368_RST_PCM                13
+
+#endif /* __DT_BINDINGS_RESET_BCM6368_H */