fix buggy constraints in mips inline syscall asm

if same register is used for input/output, the compiler must be told.
otherwise is generates random junk code that clobbers the result. in
pure syscall-wrapper functions, nothing went wrong, but in more
complex functions where register allocation is non-trivial, things
broke badly.

diff --git a/arch/mips/syscall_arch.h b/arch/mips/syscall_arch.h
index b1e68ffb59af695d96198307e1bd840485add096..7c7f9a1a655cdf13b9b8fbb03402975fc1a47de3 100644 (file)
--- a/arch/mips/syscall_arch.h
+++ b/arch/mips/syscall_arch.h
@@ -11,7 +11,7 @@
        register long r2 __asm__("$2"); \
        __asm__ __volatile__ ( \
        "addu $2,$0,%2 ; syscall" \
-       : "=&r"(r2), "=r"(r7) : "ir"(n), __VA_ARGS__, "r"(r2) \
+       : "=&r"(r2), "=r"(r7) : "ir"(n), __VA_ARGS__, "0"(r2), "1"(r7) \
        : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13", \
          "$14", "$15", "$24", "$25", "hi", "lo", "memory"); \
        return r7 ? -r2 : r2; \
@@ -53,7 +53,7 @@ static inline long __syscall4(long n, long a, long b, long c, long d)
        register long r5 __asm__("$5") = b;
        register long r6 __asm__("$6") = c;
        register long r7 __asm__("$7") = d;
-       __asm_syscall("r"(r4), "r"(r5), "r"(r6), "r"(r7));
+       __asm_syscall("r"(r4), "r"(r5), "r"(r6));
 }
 
 #else