arm64: zynqmp: Rename zc1275 to zcu1275

Name of this platform has changed and released to customers that's why
name has also changed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: uboot

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b437f7500cc1c0aacff40e799795ad5e41516391..ff181978de5639916b444d01c30451a4528bc4e3 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -253,10 +253,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
        zynqmp-zcu104-revC.dtb                  \
        zynqmp-zcu106-revA.dtb                  \
        zynqmp-zcu111-revA.dtb                  \
+       zynqmp-zcu1275-revA.dtb                 \
+       zynqmp-zcu1275-revB.dtb                 \
        zynqmp-zc1232-revA.dtb                  \
        zynqmp-zc1254-revA.dtb                  \
-       zynqmp-zc1275-revA.dtb                  \
-       zynqmp-zc1275-revB.dtb                  \
        zynqmp-zc1751-xm015-dc1.dtb             \
        zynqmp-zc1751-xm016-dc2.dtb             \
        zynqmp-zc1751-xm017-dc3.dtb             \

diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zc1275-revA.dts
deleted file mode 100644 (file)
index 82c30a3..0000000
--- a/arch/arm/dts/zynqmp-zc1275-revA.dts
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * dts file for Xilinx ZynqMP ZC1275
- *
- * (C) Copyright 2017 - 2018, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-clk-ccf.dtsi"
-
-/ {
-       model = "ZynqMP ZC1275 RevA";
-       compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
-
-       aliases {
-               serial0 = &uart0;
-               serial1 = &dcc;
-               spi0 = &qspi;
-       };
-
-       chosen {
-               bootargs = "earlycon";
-               stdout-path = "serial0:115200n8";
-       };
-
-       memory@0 {
-               device_type = "memory";
-               reg = <0x0 0x0 0x0 0x80000000>;
-       };
-};
-
-&dcc {
-       status = "okay";
-};
-
-&qspi {
-       status = "okay";
-       flash@0 {
-               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-               #address-cells = <1>;
-               #size-cells = <1>;
-               reg = <0x0>;
-               spi-tx-bus-width = <1>;
-               spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
-               spi-max-frequency = <108000000>; /* Based on DC1 spec */
-               partition@qspi-fsbl-uboot { /* for testing purpose */
-                       label = "qspi-fsbl-uboot";
-                       reg = <0x0 0x100000>;
-               };
-               partition@qspi-linux { /* for testing purpose */
-                       label = "qspi-linux";
-                       reg = <0x100000 0x500000>;
-               };
-               partition@qspi-device-tree { /* for testing purpose */
-                       label = "qspi-device-tree";
-                       reg = <0x600000 0x20000>;
-               };
-               partition@qspi-rootfs { /* for testing purpose */
-                       label = "qspi-rootfs";
-                       reg = <0x620000 0x5E0000>;
-               };
-       };
-};
-
-&uart0 {
-       status = "okay";
-};

diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zc1275-revB.dts
deleted file mode 100644 (file)
index 0473503..0000000
--- a/arch/arm/dts/zynqmp-zc1275-revB.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * dts file for Xilinx ZynqMP ZC1275 RevB
- *
- * (C) Copyright 2018, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-clk-ccf.dtsi"
-
-/ {
-       model = "ZynqMP ZC1275 RevB";
-       compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
-
-       aliases {
-               serial0 = &uart0;
-               serial1 = &dcc;
-               spi0 = &qspi;
-               mmc0 = &sdhci1;
-       };
-
-       chosen {
-               bootargs = "earlycon";
-               stdout-path = "serial0:115200n8";
-       };
-
-       memory@0 {
-               device_type = "memory";
-               reg = <0x0 0x0 0x0 0x80000000>;
-       };
-};
-
-&dcc {
-       status = "okay";
-};
-
-&qspi {
-       status = "okay";
-       flash@0 {
-               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-               #address-cells = <1>;
-               #size-cells = <1>;
-               reg = <0x0>;
-               spi-tx-bus-width = <1>;
-               spi-rx-bus-width = <1>;
-               spi-max-frequency = <108000000>; /* Based on DC1 spec */
-               partition@qspi-fsbl-uboot { /* for testing purpose */
-                       label = "qspi-fsbl-uboot";
-                       reg = <0x0 0x100000>;
-               };
-               partition@qspi-linux { /* for testing purpose */
-                       label = "qspi-linux";
-                       reg = <0x100000 0x500000>;
-               };
-               partition@qspi-device-tree { /* for testing purpose */
-                       label = "qspi-device-tree";
-                       reg = <0x600000 0x20000>;
-               };
-               partition@qspi-rootfs { /* for testing purpose */
-                       label = "qspi-rootfs";
-                       reg = <0x620000 0x5E0000>;
-               };
-       };
-};
-
-&uart0 {
-       status = "okay";
-};
-
-&sdhci1 {
-       status = "okay";
-       no-1-8-v;
-       xlnx,mio_bank = <1>;
-};

diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
new file mode 100644 (file)
index 0000000..c22de57
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU1275
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+       model = "ZynqMP ZCU1275 RevA";
+       compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
+                    "xlnx,zynqmp";
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &dcc;
+               spi0 = &qspi;
+       };
+
+       chosen {
+               bootargs = "earlycon";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+};
+
+&dcc {
+       status = "okay";
+};
+
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+               partition@qspi-fsbl-uboot { /* for testing purpose */
+                       label = "qspi-fsbl-uboot";
+                       reg = <0x0 0x100000>;
+               };
+               partition@qspi-linux { /* for testing purpose */
+                       label = "qspi-linux";
+                       reg = <0x100000 0x500000>;
+               };
+               partition@qspi-device-tree { /* for testing purpose */
+                       label = "qspi-device-tree";
+                       reg = <0x600000 0x20000>;
+               };
+               partition@qspi-rootfs { /* for testing purpose */
+                       label = "qspi-rootfs";
+                       reg = <0x620000 0x5E0000>;
+               };
+       };
+};
+
+&uart0 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
new file mode 100644 (file)
index 0000000..34c4bec
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU1275 RevB
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+       model = "ZynqMP ZCU1275 RevB";
+       compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
+                    "xlnx,zynqmp";
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &dcc;
+               spi0 = &qspi;
+               mmc0 = &sdhci1;
+       };
+
+       chosen {
+               bootargs = "earlycon";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+};
+
+&dcc {
+       status = "okay";
+};
+
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+               partition@qspi-fsbl-uboot { /* for testing purpose */
+                       label = "qspi-fsbl-uboot";
+                       reg = <0x0 0x100000>;
+               };
+               partition@qspi-linux { /* for testing purpose */
+                       label = "qspi-linux";
+                       reg = <0x100000 0x500000>;
+               };
+               partition@qspi-device-tree { /* for testing purpose */
+                       label = "qspi-device-tree";
+                       reg = <0x600000 0x20000>;
+               };
+               partition@qspi-rootfs { /* for testing purpose */
+                       label = "qspi-rootfs";
+                       reg = <0x620000 0x5E0000>;
+               };
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&sdhci1 {
+       status = "okay";
+       no-1-8-v;
+       xlnx,mio_bank = <1>;
+};

diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig
deleted file mode 100644 (file)
index ed6c1b8..0000000
--- a/configs/xilinx_zynqmp_zc1275_revA_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
-CONFIG_SPL_DM=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_MISC=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig
deleted file mode 100644 (file)
index 0c2491a..0000000
--- a/configs/xilinx_zynqmp_zc1275_revB_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_MISC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig
new file mode 100644 (file)
index 0000000..c73a97a
--- /dev/null
+++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_TEXT_BASE=0xfffc0000
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revA"
+CONFIG_SPL_DM=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig
new file mode 100644 (file)
index 0000000..0d4302e
--- /dev/null
+++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_TEXT_BASE=0xfffc0000
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y