85xx: Socrates: Major code update.
authorDetlev Zundel <dzu@denx.de>
Fri, 15 Aug 2008 13:42:12 +0000 (15:42 +0200)
committerWolfgang Denk <wd@denx.de>
Tue, 9 Sep 2008 08:13:57 +0000 (10:13 +0200)
- Update the local bus ranges in the FDT for Linux for the various
  devices connected to the local bus via chip-select.

- Set the LCRR_DBYP bit in the LCRR for local bus frequencies
  lower than 66 MHz and uses I/O accessor functions consequently.

- UPM data update.

- Update of default environment and configuration.  Use I2C multibus
  as we do have two I2C buses.  Also enable sdram and ext2 commands.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
board/socrates/socrates.c
board/socrates/upm_table.h
include/configs/socrates.h

index d791f1135f1036614a264c03af3dcad39b3f1243..63694a73d21e1f01de41a46ae60a1e94be4c7938 100644 (file)
@@ -37,9 +37,8 @@
 #include <fdt_support.h>
 #include <asm/io.h>
 
-#if defined(CFG_FPGA_BASE)
 #include "upm_table.h"
-#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[];      /* FLASH chips info */
@@ -50,6 +49,7 @@ ulong flash_get_size (ulong base, int banknum);
 int checkboard (void)
 {
        volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
        char *src;
        int f;
        char *s = getenv("serial#");
@@ -79,10 +79,6 @@ int checkboard (void)
         * Initialize local bus.
         */
        local_bus_init ();
-#if defined(CFG_FPGA_BASE)
-       /* Init UPMA for FPGA access */
-       upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
-#endif
        return 0;
 }
 
@@ -149,15 +145,34 @@ int misc_init_r (void)
  */
 void local_bus_init (void)
 {
-
        volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
        volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+       sys_info_t sysinfo;
+       uint clkdiv;
+       uint lbc_mhz;
+       uint lcrr = CFG_LBC_LCRR;
+
+       get_sys_info (&sysinfo);
+       clkdiv = lbc->lcrr & 0x0f;
+       lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+       /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
+       if (lbc_mhz >= 66)
+               lcrr &= ~LCRR_DBYP;     /* DLL Enabled */
+       else
+               lcrr |= LCRR_DBYP;      /* DLL Bypass */
+
+       out_be32 (&lbc->lcrr, lcrr);
+       asm ("sync;isync;msync");
 
-       lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
-       lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
-       ecm->eedr = 0xffffffff;         /* Clear ecm errors */
-       ecm->eeer = 0xffffffff;         /* Enable ecm errors */
+       out_be32 (&lbc->ltesr, 0xffffffff);     /* Clear LBC error interrupts */
+       out_be32 (&lbc->lteir, 0xffffffff);     /* Enable LBC error interrupts */
+       out_be32 (&ecm->eedr, 0xffffffff);      /* Clear ecm errors */
+       out_be32 (&ecm->eeer, 0xffffffff);      /* Enable ecm errors */
 
+       /* Init UPMA for FPGA access */
+       out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
+       upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
 }
 
 #if defined(CONFIG_PCI)
@@ -197,9 +212,14 @@ void pci_init_board (void)
 #ifdef CONFIG_BOARD_EARLY_INIT_R
 int board_early_init_r (void)
 {
-#ifdef CONFIG_PS2MULT
-       ps2mult_early_init();
-#endif /* CONFIG_PS2MULT */
+       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+       /* set and reset the GPIO pin 2 which will reset the W83782G chip */
+       out_8((unsigned char*)&gur->gpoutdr, 0x3F );
+       out_be32((unsigned int*)&gur->gpiocr, 0x200 );  /* enable GPOut */
+       udelay(200);
+       out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
+
        return (0);
 }
 #endif /* CONFIG_BOARD_EARLY_INIT_R */
@@ -208,31 +228,27 @@ int board_early_init_r (void)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-       u32 val[4];
-       int rc;
+       u32 val[12];
+       int rc, i = 0;
 
        ft_cpu_setup(blob, bd);
 
-       /* Fixup NOR mapping */
-       val[0] = 0;                             /* chip select number */
-       val[1] = 0;                             /* always 0 */
-       val[2] = gd->bd->bi_flashstart;
-       val[3] = gd->bd->bi_flashsize;
+       /* Fixup NOR FLASH mapping */
+       val[i++] = 0;                           /* chip select number */
+       val[i++] = 0;                           /* always 0 */
+       val[i++] = gd->bd->bi_flashstart;
+       val[i++] = gd->bd->bi_flashsize;
 
-       rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
-                                 val, sizeof(val), 1);
-       if (rc)
-               printf("Unable to update property NOR mapping, err=%s\n",
-                      fdt_strerror(rc));
+       /* Fixup FPGA mapping */
+       val[i++] = 3;                           /* chip select number */
+       val[i++] = 0;                           /* always 0 */
+       val[i++] = CFG_FPGA_BASE;
+       val[i++] = CFG_FPGA_SIZE;
 
-#if defined (CFG_FPGA_BASE)
-       memset(val, 0, sizeof(val));
-       val[0] = CFG_FPGA_BASE;
-       rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg",
-                                 val, sizeof(val), 1);
+       rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+                                 val, i * sizeof(u32), 1);
        if (rc)
-               printf("Unable to update property \"fpga\", err=%s\n",
+               printf("Unable to update localbus ranges, err=%s\n",
                       fdt_strerror(rc));
-#endif
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
index ea64a59a0cb56f746f8e81f0e6336303d071cabe..ed8f887cb09c96f581db7b244aaef3c07d105669 100644 (file)
 /* UPM Table Configuration Code for FPGA access */
 static const unsigned int UPMTableA[] =
 {
-       0x00fcfc00,  0x00fcfc00,  0x00fcfc00,  0x00fcfc00, /* Words  0 to  3 */
-       0x00fcfc00,  0x00fcfc00,  0x00fcfc00,  0x00fcfc05, /* Words  4 to  7 */
-       0x00fcfc00,  0x00fcfc00,  0x00fcfc04,  0x00fcfc04, /* Words  8 to 11 */
-       0x00fcfc04,  0x00fcfc04,  0x00fcfc04,  0x00fcfc04, /* Words 12 to 15 */
-       0x00fcfc04,  0x00fcfc04,  0x00fcfc00,  0xfffffc00, /* Words 16 to 19 */
-       0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 20 to 23 */
-       0x0ffffc00,  0x0ffffc00,  0x0ffffc00,  0x00f3fc04, /* Words 24 to 27 */
-       0x0ffffc00,  0xfffffc01,  0xfffffc00,  0xfffffc01, /* Words 28 to 31 */
-       0x0ffffc00,  0x00f3fc04,  0x00f3fc04,  0x00f3fc04, /* Words 32 to 35 */
-       0x00f3fc04,  0x00f3fc04,  0x00f3fc04,  0x00f3fc04, /* Words 36 to 39 */
-       0x00f3fc04,  0x0ffffc00,  0xfffffc00,  0xfffffc00, /* Words 40 to 43 */
-       0xfffffc01,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 44 to 47 */
-       0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 48 to 51 */
-       0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 52 to 55 */
-       0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 56 to 59 */
-       0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01  /* Words 60 to 63 */
+       0x00fcec00,  0x00fcec00,  0x00fcec00,  0x00fcec00, /* Words 0 to 3      */
+       0x00fcec00,  0x00fcfc00,  0x00fcfc00,  0x00fcec05, /* Words 4 to 7      */
+       0x00fcec00,  0x00fcec00,  0x00fcec04,  0x00fcec04, /* Words 8 to 11     */
+       0x00fcec04,  0x00fcec04,  0x00fcec04,  0x00fcec04, /* Words 12 to 15    */
+       0x00fcec04,  0x00fcec04,  0x0fffec00,  0xffffec00, /* Words 16 to 19    */
+       0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 20 to 23    */
+       0x00ffec00,  0x00ffec00,  0x00f3ec00,  0x0fffec00, /* Words 24 to 27    */
+       0x0ffffc04,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 28 to 31    */
+       0x00ffec00,  0x00ffec00,  0x00f3ec04,  0x00f3ec04, /* Words 32 to 35    */
+       0x00f3ec04,  0x00f3ec04,  0x00f3ec04,  0x00f3ec04, /* Words 36 to 39    */
+       0x00f3ec04,  0x00f3ec04,  0x0fffec00,  0xffffec00, /* Words 40 to 43    */
+       0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 44 to 47    */
+       0xffffec00,  0xffffec00,  0xffffec00,  0xffffec00, /* Words 48 to 51    */
+       0xffffec00,  0xffffec00,  0xffffec00,  0xffffec00, /* Words 52 to 55    */
+       0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 56 to 59    */
+       0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01  /* Words 60 to 63    */
 };
 
 #endif
index 5cc4213debcc0d7cc1f5ecd133354e83f38cb3d1..197ed78d5db185706034b370f6c79b512c962801 100644 (file)
@@ -45,6 +45,7 @@
 #define CONFIG_TSEC_ENET               /* tsec ethernet support        */
 
 #define CONFIG_MISC_INIT_R     1       /* Call misc_init_r             */
+#define CONFIG_BOARD_EARLY_INIT_R 1    /* Call board_early_init_r      */
 
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
 #define CFG_FLASH_BASE         CFG_LBC_FLASH_BASE /* start of FLASH    */
 
 #define CFG_BR0_PRELIM         0xfe001001      /* port size 16bit      */
-#define CFG_OR0_PRELIM         0xfe000ff7      /* 32MB Flash           */
+#define CFG_OR0_PRELIM         0xfe000030      /* 32MB Flash           */
 #define CFG_BR1_PRELIM         0xfc001001      /* port size 16bit      */
-#define CFG_OR1_PRELIM         0xfe000ff7      /* 32MB Flash           */
+#define CFG_OR1_PRELIM         0xfe000030      /* 32MB Flash           */
 
 #define CFG_FLASH_CFI                          /* flash is CFI compat. */
 #define CONFIG_FLASH_CFI_DRIVER                        /* Use common CFI driver*/
-#define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector   */
 
 #define CFG_MAX_FLASH_BANKS    2               /* number of banks      */
 #define CFG_MAX_FLASH_SECT     256             /* sectors per device   */
 
 #define CFG_MONITOR_BASE       TEXT_BASE       /* start of monitor     */
 
-#define CFG_LBC_LCRR           0x00030008    /* LB clock ratio reg     */
+#define CFG_LBC_LCRR           0x00030004    /* LB clock ratio reg     */
 #define CFG_LBC_LBCR           0x00000000    /* LB config reg          */
 #define CFG_LBC_LSRT           0x20000000    /* LB sdram refresh timer */
 #define CFG_LBC_MRTPR          0x20000000    /* LB refresh timer presc.*/
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256kB for Mon*/
-#define CFG_MALLOC_LEN         (256 * 1024)    /* Reserved for malloc  */
+#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256kB for Mon */
+#define CFG_MALLOC_LEN         (4 << 20)       /* Reserve 4 MB for malloc */
+
+/* FPGA and NAND */
+#define CFG_FPGA_BASE          0xc0000000
+#define CFG_FPGA_SIZE          0x00100000      /* 1 MB         */
+#define CFG_HMI_BASE           0xc0010000
+#define CFG_BR3_PRELIM         0xc0001881      /* UPMA, 32-bit */
+#define CFG_OR3_PRELIM         0xfff00000      /* 1 MB         */
+
+#define CFG_NAND_BASE          (CFG_FPGA_BASE + 0x70)
+#define CFG_MAX_NAND_DEVICE    1
+#define NAND_MAX_CHIPS         1
+#define CONFIG_CMD_NAND
 
 /* Serial Port */
 
 #define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C                        /* I2C with hardware support    */
 #undef CONFIG_SOFT_I2C                 /* I2C bit-banged               */
-#define CFG_I2C_SPEED          400000  /* I2C speed and slave address  */
+#define CFG_I2C_SPEED          102124  /* I2C speed and slave address  */
 #define CFG_I2C_SLAVE          0x7F
-#define CFG_I2C_NOPROBES       {0x48}  /* Don't probe these addrs      */
 #define CFG_I2C_OFFSET         0x3000
 
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C2_OFFSET                0x3100
+
 /* I2C RTC */
 #define CONFIG_RTC_RX8025              /* Use Epson rx8025 rtc via i2c */
 #define CFG_I2C_RTC_ADDR       0x32    /* at address 0x32              */
 #define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
-
+#define CONFIG_CMD_EXT2                /* EXT2 Support                 */
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
 #endif
 
-
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 /*
 
 #define CONFIG_LOADADDR         200000         /* default addr for tftp & bootm*/
 
-#define CONFIG_BOOTDELAY 5             /* -1 disables auto-boot        */
+#define CONFIG_BOOTDELAY 1             /* -1 disables auto-boot        */
 
 #define CONFIG_PREBOOT "echo;" \
-       "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+       "echo Welcome on the ABB Socrates Board;" \
        "echo"
 
 #undef CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 
 #define        CONFIG_EXTRA_ENV_SETTINGS                                       \
-       "bootfile=$hostname/uImage\0"                                   \
        "netdev=eth0\0"                                                 \
        "consdev=ttyS0\0"                                               \
-       "hostname=socrates\0"                                           \
+       "uboot_file=/home/tftp/syscon3/u-boot.bin\0"                    \
+       "bootfile=/home/tftp/syscon3/uImage\0"                          \
+       "fdt_file=/home/tftp/syscon3/socrates.dtb\0"                    \
+       "initrd_file=/home/tftp/syscon3/uinitrd.gz\0"                   \
+       "uboot_addr=FFFA0000\0"                                         \
+       "kernel_addr=FE000000\0"                                        \
+       "fdt_addr=FE1E0000\0"                                           \
+       "ramdisk_addr=FE200000\0"                                       \
+       "fdt_addr_r=B00000\0"                                           \
+       "kernel_addr_r=200000\0"                                        \
+       "ramdisk_addr_r=400000\0"                                       \
+       "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
+       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
                "nfsroot=$serverip:$rootpath\0"                         \
-       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+       "addcons=setenv bootargs $bootargs "                            \
+               "console=$consdev,$baudrate\0"                          \
        "addip=setenv bootargs $bootargs "                              \
                "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
                ":$hostname:$netdev:off panic=1\0"                      \
-       "addcons=setenv bootargs $bootargs "                            \
-               "console=$consdev,$baudrate\0"                          \
-       "flash_self=run ramargs addip addcons;"                         \
+       "boot_nor=run ramargs addcons;"                                 \
                "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
-       "flash_nfs=run nfsargs addip addcons;"                          \
-               "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
        "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
                "tftp ${fdt_addr_r} ${fdt_file}; "                      \
                "run nfsargs addip addcons;"                            \
                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
-       "fdt_file=$hostname/socrates.dtb\0"                             \
-       "fdt_addr_r=B00000\0"                                           \
-       "fdt_addr=FC1E0000\0"                                           \
-       "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
-       "kernel_addr=FC000000\0"                                        \
-       "kernel_addr_r=200000\0"                                        \
-       "ramdisk_addr=FC200000\0"                                       \
-       "ramdisk_addr_r=400000\0"                                       \
-       "load=tftp 100000 $hostname/u-boot.bin\0"               \
-       "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
-               "cp.b 100000 fffc0000 40000;"                           \
+       "update_uboot=tftp 100000 ${uboot_file};"                       \
+               "protect off fffa0000 ffffffff;"                        \
+               "era fffa0000 ffffffff;"                                \
+               "cp.b 100000 fffa0000 ${filesize};"                     \
+               "setenv filesize;saveenv\0"                             \
+       "update_kernel=tftp 100000 ${bootfile};"                        \
+               "era fe000000 fe1dffff;"                                \
+               "cp.b 100000 fe000000 ${filesize};"                     \
                "setenv filesize;saveenv\0"                             \
-       "upd=run load update\0"                                         \
+       "update_fdt=tftp 100000 ${fdt_file};"                           \
+               "era fe1e0000 fe1fffff;"                                \
+               "cp.b 100000 fe1e0000 ${filesize};"                     \
+               "setenv filesize;saveenv\0"                             \
+       "update_initrd=tftp 100000 ${initrd_file};"                     \
+               "era fe200000 fe9fffff;"                                \
+               "cp.b 100000 fe200000 ${filesize};"                     \
+               "setenv filesize;saveenv\0"                             \
+       "clean_data=era fea00000 fff5ffff\0"                            \
+       "usbargs=setenv bootargs root=/dev/sda1 rw\0"                   \
+       "load_usb=usb start;"                                           \
+               "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"      \
+       "boot_usb=run load_usb usbargs addcons;"                        \
+               "bootm ${kernel_addr_r} - ${fdt_addr};"                 \
+               "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
        ""
-#define CONFIG_BOOTCOMMAND     "run flash_self"
+#define CONFIG_BOOTCOMMAND     "run boot_nor"
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1
 #define CONFIG_DOS_PARTITION           1
 #define CONFIG_USB_STORAGE             1
 
-/* FPGA and NAND */
-#define CFG_FPGA_BASE                  0xc0000000
-#define CFG_BR3_PRELIM                 0xc0001881 /* UPMA, 32-bit */
-#define CFG_OR3_PRELIM                 0xfff00000  /* 1 MB */
-
-#define CFG_NAND_BASE                  (CFG_FPGA_BASE + 0x70)
-#define CFG_MAX_NAND_DEVICE            1
-#define NAND_MAX_CHIPS                 1
-#define CONFIG_CMD_NAND
-
 #endif /* __CONFIG_H */