spi: mxc_spi: Fix spi clock glitch durant reset

Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.

Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index b6bad989527b75b6e94d1f1184e929a66203e9e1..859c43fee2790de7c80335bb58a71b20934c49f9 100644 (file)
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -140,8 +140,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
        reg_ctrl = reg_read(&regs->ctrl);
 
        /* Reset spi */
-       reg_write(&regs->ctrl, 0);
-       reg_write(&regs->ctrl, (reg_ctrl | 0x1));
+       reg_write(&regs->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
+       reg_write(&regs->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
 
        /*
         * The following computation is taken directly from Freescale's code.