Add functions which return DDR width and CAS latency, use them in printing board...

diff --git a/u-boot/board/ar7240/common/common.c b/u-boot/board/ar7240/common/common.c
index 3f9ed0e38a6ff5da6eb62e9ec18be78a7e721752..60f76a38a1e958852076f7c85da8228e4a90cbfe 100644 (file)
--- a/u-boot/board/ar7240/common/common.c
+++ b/u-boot/board/ar7240/common/common.c
@@ -107,19 +107,24 @@ void print_board_info(void)
 
        switch (qca_dram_type()) {
        case RAM_MEMORY_TYPE_SDR:
-               puts(" SDR\n");
+               puts(" SDR ");
                break;
        case RAM_MEMORY_TYPE_DDR1:
-               puts(" DDR1\n");
+               puts(" DDR1 ");
                break;
        case RAM_MEMORY_TYPE_DDR2:
-               puts(" DDR2\n");
+               puts(" DDR2 ");
                break;
        default:
-               puts("\n");
                break;
        }
 
+       /* DDR interface width */
+       printf("%d-bit ", qca_dram_ddr_width());
+
+       /* CAS latency */
+       printf("CL%d\n", qca_dram_cas_lat());
+
        /* SPI NOR FLASH sizes and types */
        printf("%" ALIGN_SIZE "s ", "FLASH:");
 

diff --git a/u-boot/cpu/mips/ar7240/qca_dram.c b/u-boot/cpu/mips/ar7240/qca_dram.c
index 2cfc7a5153426d8c5951e8c491a30db9931607fe..4723ce3847324870562dc1fd339901af5c6ef7ed 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_dram.c
+++ b/u-boot/cpu/mips/ar7240/qca_dram.c
@@ -91,3 +91,40 @@ u32 qca_dram_type(void)
        return dram_type;
 #endif
 }
+
+/*
+ * Returns DDR width (16 or 32)
+ */
+u32 qca_dram_ddr_width(void)
+{
+#ifndef CONFIG_BOARD_DRAM_DDR_WIDTH
+       if (qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG)
+               & QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK)
+               return 32;
+
+       return 16;
+#else
+       return CONFIG_BOARD_DRAM_DDR_WIDTH;
+#endif
+}
+
+/*
+ * Returns CAS latency, based on setting in DDR_CONFIG register
+ */
+u32 qca_dram_cas_lat(void)
+{
+#ifndef CONFIG_BOARD_DRAM_CAS_LATENCY
+       u32 reg;
+
+       reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_CAS_3LSB_MASK)
+                 >> QCA_DDR_CFG_CAS_3LSB_SHIFT;
+
+       if (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_CAS_MSB_MASK)
+               reg = reg + 8;
+
+       /* CAS_LATENCY value in DDR_CONFIG register == 2 * MEM_CAS */
+       return reg / 2;
+#else
+       return CONFIG_BOARD_DRAM_CAS_LATENCY
+#endif
+}