NET: Base support for etsec2.0
authorKumar Gala <galak@kernel.crashing.org>
Sat, 31 Oct 2009 16:23:41 +0000 (11:23 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 5 Jan 2010 19:49:04 +0000 (13:49 -0600)
1. Modified the tsec_mdio structure to include the new regs
2. Modified the MDIO_BASE_ADDR so that it will handle both
older version and new version of etsec.

Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
include/asm-ppc/config.h
include/asm-ppc/immap_83xx.h
include/asm-ppc/immap_85xx.h
include/asm-ppc/immap_86xx.h
include/tsec.h

index af0853b0d7e9fd5f65377992dce354369cbb0a36..d5f82b44f3890ec03562a2ce62030a4e8f5771f5 100644 (file)
 #endif
 #endif
 
+/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
+#if defined(CONFIG_TSEC_ENET) && \
+    (defined(CONFIG_P1020) || defined(CONFIG_P1011))
+#define CONFIG_TSECV2
+#endif
+
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
index 3a144f0402c901e09cd6e7e803ed292b52fae11c..6b42a73f3f6fc802c7c82ae3fc4a3c41ea299ed9 100644 (file)
@@ -870,7 +870,7 @@ typedef struct immap {
                        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
 
 #define CONFIG_SYS_TSEC1_OFFSET                0x24000
-#define CONFIG_SYS_MDIO1_OFFSET                0x24520
+#define CONFIG_SYS_MDIO1_OFFSET                0x24000
 
 #define TSEC_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
index 3d24ebe4cee0e4dd35406577a07739698bfa147d..43b3a2c71061e3b936ac743ce4594aed3dedd7d8 100644 (file)
@@ -1959,8 +1959,12 @@ enum {
 #define CONFIG_SYS_MPC85xx_L2_OFFSET           0x20000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET          0x21000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET          0x22000
+#ifdef CONFIG_TSECV2
+#define CONFIG_SYS_TSEC1_OFFSET                        0xB0000
+#else
 #define CONFIG_SYS_TSEC1_OFFSET                        0x24000
-#define CONFIG_SYS_MDIO1_OFFSET                        0x24520
+#endif
+#define CONFIG_SYS_MDIO1_OFFSET                        0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET                0x2e000
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
index 41892b4e5d621f855ac8ba21a45f783e406228c0..098f25384b7b5ee568beb96f43f71a83f62a60b7 100644 (file)
@@ -1299,7 +1299,7 @@ extern immap_t  *immr;
 #define CONFIG_SYS_MPC86xx_DMA_ADDR    (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
 
 #define CONFIG_SYS_TSEC1_OFFSET                0x24000
-#define CONFIG_SYS_MDIO1_OFFSET                0x24520
+#define CONFIG_SYS_MDIO1_OFFSET                0x24000
 
 #define TSEC_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
index 92bd028f0ead30ea6136b7b5c83259b85c610339..f56723a153508d7f9f85384616bb891992f203dd 100644 (file)
@@ -457,12 +457,19 @@ typedef struct tsec_hash_regs
 } tsec_hash_t;
 
 typedef struct tsec_mdio {
+       uint    res1[4];
+       uint    ieventm;
+       uint    imaskm;
+       uint    res2;
+       uint    emapm;
+       uint    res3[320];
        uint    miimcfg;        /* MII Management: Configuration */
        uint    miimcom;        /* MII Management: Command */
        uint    miimadd;        /* MII Management: Address */
        uint    miimcon;        /* MII Management: Control */
        uint    miimstat;       /* MII Management: Status */
        uint    miimind;        /* MII Management: Indicators */
+       uint    res4[690];
 } tsec_mdio_t;
 
 typedef struct tsec