DRA7: Add support for ES1.1 silicon ID code
authorNishanth Menon <nm@ti.com>
Tue, 14 Jan 2014 16:54:42 +0000 (10:54 -0600)
committerTom Rini <trini@ti.com>
Fri, 24 Jan 2014 16:41:17 +0000 (11:41 -0500)
ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support
for ES1.1 IDCODE change.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/omap_common.h

index cd6289b4fca0827e40819be8f7253137c25d8f18..429c4becf3469e7061abc08e6799f54d48c62ff5 100644 (file)
@@ -179,8 +179,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
        writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-       if ((omap_revision() >= OMAP5430_ES1_0) ||
-                               (omap_revision() == DRA752_ES1_0)) {
+       if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
                writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
                        &emif->emif_l3_config);
        } else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -309,7 +308,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
         * The same sequence should work on OMAP5432 as well. But strange that
         * it is not working
         */
-       if (omap_revision() == DRA752_ES1_0) {
+       if (is_dra7xx()) {
                do_ext_phy_settings(base, regs);
                writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
                writel(regs->sdram_config_init, &emif->emif_sdram_config);
index 32998aabb94634fc035b66339883c7b003b57a92..ad971327bf223b7f1e02ee729b5a8dc07813fecc 100644 (file)
@@ -551,6 +551,7 @@ void hw_data_init(void)
        break;
 
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra7xx_dplls;
        *omap_vcores = &dra752_volts;
@@ -578,6 +579,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
                *regs = &ioregs_omap5432_es2;
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                *regs = &ioregs_dra7xx_es1;
                break;
 
index 5386ae0568b31f7489f0669692ba441ea50eaeba..737d23ccb4316e931a134afc6ecd80a638af4cfb 100644 (file)
@@ -333,6 +333,9 @@ void init_omap_revision(void)
        case DRA752_CONTROL_ID_CODE_ES1_0:
                *omap_si_rev = DRA752_ES1_0;
                break;
+       case DRA752_CONTROL_ID_CODE_ES1_1:
+               *omap_si_rev = DRA752_ES1_1;
+               break;
        default:
                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
        }
index 2e1870609a4b78589ef2f3d456d320ec08f372b0..16a91f911a0c84bedadfd2e8010f612618b60b00 100644 (file)
@@ -245,6 +245,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                switch (emif_nr) {
                case 1:
                        *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
@@ -273,6 +274,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
                *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
        default:
                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
        }
@@ -460,6 +462,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =
@@ -626,6 +629,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
                             sizeof(omap5_bug_00339_regs[0]);
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                bug_00339_regs_ptr = dra_bug_00339_regs;
                *iterations = sizeof(dra_bug_00339_regs)/
                             sizeof(dra_bug_00339_regs[0]);
index 590235be098967bdb4f4720a89f0de2fda590aa4..34f6fc5f3529ea81c124d5a8098e3c75c8c095f2 100644 (file)
@@ -44,6 +44,7 @@
 #define OMAP5432_CONTROL_ID_CODE_ES1_0         0x0B99802F
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0           0x0B99002F
+#define DRA752_CONTROL_ID_CODE_ES1_1           0x1B99002F
 
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
index 4efc89ee20602cc7adf66c08d2b4f0ad28a8add3..04925bca1cdfedcd8312d443ef7110c8415d8bc5 100644 (file)
@@ -642,6 +642,7 @@ static inline u8 is_dra7xx(void)
 
 /* DRA7XX */
 #define DRA752_ES1_0   0x07520100
+#define DRA752_ES1_1   0x07520110
 
 /*
  * SRAM scratch space entries