socfpga: Fix SOCFPGA build error for Altera dev kit
authorChin Liang See <clsee@altera.com>
Tue, 22 Jul 2014 09:28:35 +0000 (04:28 -0500)
committerTom Rini <trini@ti.com>
Fri, 29 Aug 2014 19:50:54 +0000 (15:50 -0400)
To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtual target. With that, U-Boot
is booting well and SPL still lack of few drivers.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
arch/arm/cpu/armv7/socfpga/clock_manager.c
arch/arm/cpu/armv7/socfpga/config.mk
arch/arm/cpu/armv7/socfpga/spl.c
arch/arm/include/asm/arch-socfpga/scan_manager.h
board/altera/socfpga/Makefile
include/configs/socfpga_cyclone5.h

index 0228ac8c3b5e36db6c7e4a88a816252455b149c7..158501acba8c84b0681d8011181bf3484b205c51 100644 (file)
@@ -188,7 +188,6 @@ void cm_basic_init(const cm_config_t *cfg)
         * Time starts here
         * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
         */
-       reset_timer();
        start = get_timer(0);
        /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
        timeout = 7;
index 3d18491577f2ec845787ffcd30c88c532e097062..2a99c72aeb88adbdc592a1c2447fc769be39736f 100644 (file)
@@ -6,3 +6,6 @@
 ifndef CONFIG_SPL_BUILD
 ALL-y  += u-boot.img
 endif
+
+# Added for handoff support
+PLATFORM_RELFLAGS += -Iboard/$(VENDOR)/$(BOARD)
index 4bed19d0a75c01d6c32bbfc621fa896b1a27fa5c..27efde62cca1e3925294567afedc5a30dfe2706f 100644 (file)
@@ -14,6 +14,8 @@
 #include <spl.h>
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/scan_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
index f9be6211b3d16522b78246aa9a5b2d4fc423300a..b2686d3cdb68f74479dfbb3f68ba1fa6dab5d262 100644 (file)
@@ -87,4 +87,6 @@ extern const uint32_t iocsr_scan_chain2_table[
 extern const uint32_t iocsr_scan_chain3_table[
        ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)];
 
+int scan_mgr_configure_iocsr(void);
+
 #endif /* _SCAN_MANAGER_H_ */
index de339ec7f7e65774585ef75bef31a82d4f39518e..44baa0068cc2d990ba384835d92f554fc8884555 100644 (file)
@@ -7,4 +7,4 @@
 #
 
 obj-y  := socfpga_cyclone5.o
-obj-$(CONFIG_SPL_BUILD) += pinmux_config.o
+obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
index 27c2be909831a24681e8a001926af5e9605da0fa..e02b50a4a8d0c4f9500ca9bf2dc16fb44d935076 100644 (file)
@@ -15,7 +15,7 @@
  * High level configuration
  */
 /* Virtual target or real hardware */
-#define CONFIG_SOCFPGA_VIRTUAL_TARGET
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_ARMV7
 #define CONFIG_SYS_DCACHE_OFF