zynq: slcr: Wait 100ms till clk is properly setup
authorMichal Simek <michal.simek@xilinx.com>
Wed, 8 May 2013 13:37:28 +0000 (15:37 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 12 Aug 2013 06:59:55 +0000 (08:59 +0200)
If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
arch/arm/cpu/armv7/zynq/slcr.c

index e5fe9929827cd6117ec683d1986a804f998c9f29..717ec65aeee0132a6a07f49c774192ec18f4e4f4 100644 (file)
@@ -70,7 +70,7 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
                /* Configure GEM_RCLK_CTRL */
                writel(rclk, &slcr_base->gem0_rclk_ctrl);
        }
-
+       udelay(100000);
 out:
        zynq_slcr_lock();
 }