const uint32_t bbar_mask = 0x00ffff00;
uint32_t ichspi_bbar;
- minaddr &= bbar_mask;
- ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
- ichspi_bbar |= minaddr;
- ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
+ if (ctlr->bbar) {
+ minaddr &= bbar_mask;
+ ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
+ ichspi_bbar |= minaddr;
+ ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
+ }
}
/* @return 1 if the SPI flash supports the 33MHz speed */
ctlr->preop = offsetof(struct ich9_spi_regs, preop);
ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
ctlr->pr = &ich9_spi->pr[0];
+ } else if (plat->ich_version == ICHV_APL) {
} else {
debug("ICH SPI: Unrecognised ICH version %d\n",
plat->ich_version);
plat->ich_version = dev_get_driver_data(dev);
plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
- pch_get_spi_base(priv->pch, &plat->mmio_base);
+ if (plat->ich_version == ICHV_APL) {
+ plat->mmio_base = dm_pci_read_bar32(dev, 0);
+ } else {
+ /* SBASE is similar */
+ pch_get_spi_base(priv->pch, &plat->mmio_base);
+ }
/*
* Use an int so that the property is present in of-platdata even
* when false.
static const struct udevice_id ich_spi_ids[] = {
{ .compatible = "intel,ich7-spi", ICHV_7 },
{ .compatible = "intel,ich9-spi", ICHV_9 },
+ { .compatible = "intel,fast-spi", ICHV_APL },
{ }
};