#include <asm/arch/prcm.h>
#include <asm/arch/rsb.h>
+static int rsb_set_device_mode(void);
+
static void rsb_cfg_io(void)
{
#ifdef CONFIG_MACH_SUN8I
writel((cd_odly << 8) | div, &rsb->ccr);
}
-void rsb_init(void)
+int rsb_init(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
rsb_set_clk();
+
+ return rsb_set_device_mode();
}
static int rsb_await_trans(void)
return ret;
}
-int rsb_set_device_mode(u32 device_mode_data)
+static int rsb_set_device_mode(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
unsigned long tmo = timer_get_us() + 1000000;
- writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
+ writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
+ &rsb->dmcr);
while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
if (timer_get_us() > tmo)
#define RSB_STAT_TERR_INT (1 << 1)
#define RSB_STAT_LBSY_INT (1 << 2)
+#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00
#define RSB_DMCR_DEVICE_MODE_START (1 << 31)
#define RSB_CMD_BYTE_WRITE 0x4e
#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16)
#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0)
-void rsb_init(void);
-int rsb_set_device_mode(u32 device_mode_data);
+int rsb_init(void);
int rsb_set_device_address(u16 device_addr, u16 runtime_addr);
int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
#define AXP223_DEVICE_ADDR 0x3a3
#define AXP223_RUNTIME_ADDR 0x2d
-#define AXP223_DEVICE_MODE_DATA 0x7c3e00
/* Page 0 addresses */
#define AXP221_CHIP_ID 0x03