sun6i: Make dram clk and zq value Kconfig options

It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.

Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
index 699173cf699b252e68793190513daa65ee6f755c..8f567c6452f406a75dd188d00691a6247673da92 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
@@ -17,9 +17,7 @@
 #include <asm/arch/dram.h>
 #include <asm/arch/prcm.h>
 
-/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */
-#define DRAM_CLK_DEFAULT 312000000
-#define DRAM_ZQ_DEFAULT 0x78
+#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
 
 struct dram_sun6i_para {
        u8 bus_width;
@@ -48,7 +46,7 @@ static void mctl_sys_init(void)
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
        const int dram_clk_div = 2;
 
-       clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
+       clock_set_pll5(DRAM_CLK * dram_clk_div);
 
        clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
                CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
@@ -170,7 +168,7 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
 
        await_completion(&mctl_phy->pgsr, 0x03, 0x03);
 
-       writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1);
+       writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
 
        setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
        writel(MCTL_PIR_STEP1, &mctl_phy->pir);
@@ -216,9 +214,9 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
        await_completion(&mctl_ctl->sstat, 0x07, 0x01);
 
        /* Set number of clks per micro-second */
-       writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u);
+       writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
        /* Set number of clks per 100 nano-seconds */
-       writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n);
+       writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
        /* Set memory timing registers */
        writel(MCTL_TREFI, &mctl_ctl->trefi);
        writel(MCTL_TMRD, &mctl_ctl->tmrd);

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5ae491d7380386ec48f4aaf63fe5ec21ba6d0223..f7da7042f4cfb37d09e54d2386a26604c3440016 100644 (file)
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -32,6 +32,23 @@ config MACH_SUN8I
 
 endchoice
 
+if MACH_SUN6I
+
+config DRAM_CLK
+       int "sun6i dram clock speed"
+       default 312
+       ---help---
+       Set the dram clock speed, valid range 240 - 480, must be a multiple
+       of 24.
+
+config DRAM_ZQ
+       int "sun6i dram zq value"
+       default 123
+       ---help---
+       Set the dram zq value.
+
+endif
+
 config SYS_CONFIG_NAME
        default "sun4i" if MACH_SUN4I
        default "sun5i" if MACH_SUN5I

diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index de78a01801ed939aebaee7e0ba30f75616d3e947..9b4968fbd3287489ee491f353188aeba0f41c9a6 100644 (file)
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -5,3 +5,5 @@ CONFIG_USB_KEYBOARD=n
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN6I=y
 +S:CONFIG_TARGET_COLOMBUS=y
++S:CONFIG_DRAM_CLK=288
++S:CONFIG_DRAM_ZQ=379

diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index ac3cd36be800e4bee266706d8ea10435b1d482e3..a598254b2d11e7d2a3fa4b6c1e581d6bd3356a6e 100644 (file)
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -5,6 +5,8 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb"
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN6I=y
 +S:CONFIG_TARGET_MELE_M9=y
++S:CONFIG_DRAM_CLK=312
++S:CONFIG_DRAM_ZQ=120
 # Ethernet phy power
 +S:CONFIG_AXP221_DLDO1_VOLT=3300
 # USB hub power