imx: mx6slevk: Add support for USDHC1 and USDHC3 slots
authorYe.Li <B37916@freescale.com>
Thu, 30 Oct 2014 10:30:54 +0000 (18:30 +0800)
committerStefano Babic <sbabic@denx.de>
Mon, 3 Nov 2014 10:21:49 +0000 (11:21 +0100)
There are three SD/MMC sockets on mx6slevk boards. Implements the
full support for them.
The default boot socket is USDHC2, so the MMC environment is set
to that device.

Signed-off-by: Ye.Li <B37916@freescale.com>
board/freescale/mx6slevk/mx6slevk.c
include/configs/mx6slevk.h

index a500133efae1b08b3c416dd202bb5ef2b654c0f2..e76c343812e6de157d03a9fcd4b5336734266e65 100644 (file)
@@ -52,6 +52,23 @@ static iomux_v3_cfg_t const uart1_pads[] = {
        MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+       /* 8 bit SD */
+       MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+       /*CD pin*/
+       MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const usdhc2_pads[] = {
        MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -59,6 +76,21 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
        MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+       /*CD pin*/
+       MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+       MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+       /*CD pin*/
+       MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static iomux_v3_cfg_t const fec_pads[] = {
@@ -109,21 +141,82 @@ static void setup_iomux_fec(void)
        gpio_set_value(ETH_PHY_RESET, 1);
 }
 
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
-       {USDHC2_BASE_ADDR},
+#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       {USDHC1_BASE_ADDR},
+       {USDHC2_BASE_ADDR, 0, 4},
+       {USDHC3_BASE_ADDR, 0, 4},
 };
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-       return 1;       /* Assume boot SD always present */
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC1_BASE_ADDR:
+               ret = !gpio_get_value(USDHC1_CD_GPIO);
+               break;
+       case USDHC2_BASE_ADDR:
+               ret = !gpio_get_value(USDHC2_CD_GPIO);
+               break;
+       case USDHC3_BASE_ADDR:
+               ret = !gpio_get_value(USDHC3_CD_GPIO);
+               break;
+       }
+
+       return ret;
 }
 
 int board_mmc_init(bd_t *bis)
 {
-       imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+       int i, ret;
+
+       /*
+        * According to the board_mmc_init() the following map is done:
+        * (U-boot device node)    (Physical Port)
+        * mmc0                    USDHC1
+        * mmc1                    USDHC2
+        * mmc2                    USDHC3
+        */
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+                       gpio_direction_input(USDHC1_CD_GPIO);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+                       break;
+               case 1:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                       gpio_direction_input(USDHC2_CD_GPIO);
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+                       break;
+               case 2:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+                       gpio_direction_input(USDHC3_CD_GPIO);
+                       usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                               "(%d) than supported by the board\n", i + 1);
+                       return -EINVAL;
+                       }
+
+                       ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+                       if (ret) {
+                               printf("Warning: failed to initialize "
+                                       "mmc dev %d\n", i);
+                               return ret;
+                       }
+       }
 
-       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+       return 0;
 }
 
 #ifdef CONFIG_FEC_MXC
index fddedf1a8eb28c87ce4490407ec43144fc350a5e..4fcaf515c7bb186076a9da07a880906bc93bacaf 100644 (file)
 #define CONFIG_ENV_OFFSET              (6 * SZ_64K)
 #define CONFIG_ENV_SIZE                        SZ_8K
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV         0
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #endif
 
+#define CONFIG_SYS_FSL_USDHC_NUM       3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV         1       /* SDHC2*/
+#endif
+
 #endif                         /* __CONFIG_H */