sunxi: display: Move DDC PLL setup to HDMI init
authorPriit Laes <priit.laes@paf.com>
Wed, 19 Dec 2018 13:06:08 +0000 (15:06 +0200)
committerAnatolij Gustschin <agust@denx.de>
Fri, 15 Feb 2019 15:28:58 +0000 (16:28 +0100)
Move PLL initialization code to single place so
we won't call it every time we query for EDID data.

Signed-off-by: Priit Laes <priit.laes@paf.com>
drivers/video/sunxi/sunxi_display.c

index 6dd9bec351fb4525b357db4d75a2c1ed49db7ed5..0362071f720b877d3c40959e4374a1a14fbe55a8 100644 (file)
@@ -113,6 +113,13 @@ static int sunxi_hdmi_hpd_detect(int hpd_delay)
        writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
        writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
 
+       /* Enable PLLs for eventual DDC */
+       writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
+              &hdmi->pad_ctrl1);
+       writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
+              &hdmi->pll_ctrl);
+       writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
+
        while (timer_get_us() < tmo) {
                if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
                        return 1;
@@ -215,13 +222,6 @@ static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
        int i, r, ext_blocks = 0;
 
-       /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
-       writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
-              &hdmi->pad_ctrl1);
-       writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
-              &hdmi->pll_ctrl);
-       writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
-
        /* Reset i2c controller */
        setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
        writel(SUNXI_HMDI_DDC_CTRL_ENABLE |