davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK
authorEric Benard <eric@eukrea.com>
Mon, 22 Apr 2013 05:55:00 +0000 (05:55 +0000)
committerTom Rini <trini@ti.com>
Fri, 10 May 2013 12:25:56 +0000 (08:25 -0400)
these variables are curently defined in several config files but the
driver doesn't use them and defaults to hardcoded values in
nand_defs.h

It's interesting to be able to change this hardcoded valude when the
hardware is not using the default adress signals to drive ALE and CLE
and two configuration defines already exist for this purpose so use
them.

Signed-off-by: Eric BĂ©nard <eric@eukrea.com>
arch/arm/include/asm/arch-davinci/nand_defs.h
include/configs/da830evm.h
include/configs/da850evm.h
include/configs/enbw_cmc.h
include/configs/tnetv107x_evm.h

index 10f3a392abaf9d3abfc096073ab1ed130637a635..4a30813808afd4c09d05a9ce9bf91ebcdac2913e 100644 (file)
 #define        MASK_ALE        0x08
 #endif
 
+#ifdef CONFIG_SYS_NAND_MASK_CLE
+#undef MASK_CLE
+#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#endif
+#ifdef CONFIG_SYS_NAND_MASK_ALE
+#undef MASK_ALE
+#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#endif
+
 #define NAND_READ_START                0x00
 #define NAND_READ_END          0x30
 #define NAND_STATUS            0x70
index f7ac256a0fa5df67d0895be6027bddea37531241..198892ba571de796208417e045dc6137271b4670 100644 (file)
 #define CONFIG_SYS_NAND_CS             3
 #define CONFIG_SYS_NAND_BASE           DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 #define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_CLE_MASK            0x10
-#define CONFIG_SYS_ALE_MASK            0x8
+#define CONFIG_SYS_NAND_MASK_CLE               0x10
+#define CONFIG_SYS_NAND_MASK_ALE               0x8
 #define CONFIG_SYS_MAX_NAND_DEVICE     1 /* Max number of NAND devices */
 #endif
 
index 583568d309afc90734869bb5e07926be34e07882..c420967411db6ffe8b9284837dff0a9ee45ed870 100644 (file)
 #define        CONFIG_SYS_NAND_PAGE_2K
 #define CONFIG_SYS_NAND_CS             3
 #define CONFIG_SYS_NAND_BASE           DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_CLE_MASK            0x10
-#define CONFIG_SYS_ALE_MASK            0x8
+#define CONFIG_SYS_NAND_MASK_CLE               0x10
+#define CONFIG_SYS_NAND_MASK_ALE               0x8
 #undef CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE     1 /* Max number of NAND devices */
 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
index 2d63b670cd7c5011bad815533aef8338629f8c50..97bc9729a1bf39f28b3d7f3d500812163e20aa88 100644 (file)
 #define CONFIG_SYS_NAND_PAGE_2K
 #define CONFIG_SYS_NAND_CS             3
 #define CONFIG_SYS_NAND_BASE           DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_CLE_MASK            0x10
-#define CONFIG_SYS_ALE_MASK            0x8
+#define CONFIG_SYS_NAND_MASK_CLE               0x10
+#define CONFIG_SYS_NAND_MASK_ALE               0x8
 #undef CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE     1 /* Max number of NAND devices */
 
index d6371fce4d044418f12e3377c0c0d5c8bdb2227d..cabc06e5ba6e919442b7b13687320415b82853cb 100644 (file)
@@ -82,8 +82,8 @@
 #define CONFIG_SYS_NAND_CS             2
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_BASE           TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
-#define CONFIG_SYS_CLE_MASK            0x10
-#define CONFIG_SYS_ALE_MASK            0x8
+#define CONFIG_SYS_NAND_MASK_CLE               0x10
+#define CONFIG_SYS_NAND_MASK_ALE               0x8
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_CMD_MTDPARTS