armv8/ls2085ardb: Add eth & phy firmware loading support

Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.

Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile
index 0bfe21c1d834a7c02c2c01abe61148ed00fdb475..de383ccc0fafb1afdea73dc239e32e390333b38d 100644 (file)
--- a/board/freescale/ls2085ardb/Makefile
+++ b/board/freescale/ls2085ardb/Makefile
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y += ls2085ardb.o
+obj-y += ls2085ardb.o eth_ls2085rdb.o
 obj-y += ddr.o

diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c
new file mode 100644 (file)
index 0000000..60af079
--- /dev/null
+++ b/board/freescale/ls2085ardb/eth_ls2085rdb.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+int load_firmware_cortina(struct phy_device *phy_dev)
+{
+       if (phy_dev->drv->config)
+               return phy_dev->drv->config(phy_dev);
+
+       return 0;
+}
+
+void load_phy_firmware(void)
+{
+       int i;
+       u8 phy_addr;
+       struct phy_device *phy_dev;
+       struct mii_dev *dev;
+       phy_interface_t interface;
+
+       /*Initialize and upload firmware for all the PHYs*/
+       for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
+               interface = wriop_get_enet_if(i);
+               if (interface == PHY_INTERFACE_MODE_XGMII) {
+                       dev = wriop_get_mdio(i);
+                       phy_addr = wriop_get_phy_address(i);
+                       phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
+                                               interface);
+                       if (!phy_dev) {
+                               printf("No phydev for phyaddr %d\n", phy_addr);
+                               continue;
+                       }
+
+                       /*Flash firmware for All CS4340 PHYS */
+                       if (phy_dev->phy_id == PHY_UID_CS4340)
+                               load_firmware_cortina(phy_dev);
+               }
+       }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+       int i, interface;
+       struct memac_mdio_info mdio_info;
+       struct mii_dev *dev;
+       struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 srds_s1;
+       struct memac_mdio_controller *reg;
+
+       srds_s1 = in_le32(&gur->rcwsr[28]) &
+                               FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+       srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+       reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+       mdio_info.regs = reg;
+       mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+       /* Register the EMI 1 */
+       fm_memac_mdio_init(bis, &mdio_info);
+
+       reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+       mdio_info.regs = reg;
+       mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+       /* Register the EMI 2 */
+       fm_memac_mdio_init(bis, &mdio_info);
+
+       switch (srds_s1) {
+       case 0x2A:
+               wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+               wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+
+               break;
+       default:
+               printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+                      srds_s1);
+               break;
+       }
+
+       for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
+               interface = wriop_get_enet_if(i);
+               switch (interface) {
+               case PHY_INTERFACE_MODE_XGMII:
+                       dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+                       wriop_set_mdio(i, dev);
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
+               switch (wriop_get_enet_if(i)) {
+               case PHY_INTERFACE_MODE_XGMII:
+                       dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+                       wriop_set_mdio(i, dev);
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       /* Load CORTINA CS4340 PHY firmware */
+       load_phy_firmware();
+
+       cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+       return pci_eth_init(bis);
+}

diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index d05f2bc581e66a980b7e5ee0f2e8d1e37375a649..6cb7b1342251435bc54bbd5d63a927a83946921a 100644 (file)
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -176,19 +176,6 @@ unsigned long get_dram_size_to_hide(void)
        return dram_to_hide;
 }
 
-int board_eth_init(bd_t *bis)
-{
-       int error = 0;
-
-#ifdef CONFIG_FSL_MC_ENET
-       error = cpu_eth_init(bis);
-#endif
-
-       error = pci_eth_init(bis);
-
-       return error;
-}
-
 #ifdef CONFIG_FSL_MC_ENET
 void fdt_fixup_board_enet(void *fdt)
 {

diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 600261e42b6ab48f0e73514ff3dffb56108cf6ef..920560c64247a36fff9b1bcbf40070deafa5f3e9 100644 (file)
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -298,4 +298,27 @@ unsigned long get_board_sys_clk(void);
        "kernel_load=0xa0000000\0"              \
        "kernel_size=0x1000000\0"
 
+/* MAC/PHY configuration */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHYLIB
+#define        CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_CORTINA_FW_ADDR         0x581000000
+#define CONFIG_CORTINA_FW_LENGTH       0x40000
+
+#define CORTINA_PHY_ADDR1      0x10
+#define CORTINA_PHY_ADDR2      0x11
+#define CORTINA_PHY_ADDR3      0x12
+#define CORTINA_PHY_ADDR4      0x13
+#define AQ_PHY_ADDR1           0x00
+#define AQ_PHY_ADDR2           0x01
+#define AQ_PHY_ADDR3           0x02
+#define AQ_PHY_ADDR4           0x03
+
+#define CONFIG_MII
+#define CONFIG_ETHPRIME                "DPNI1"
+#define CONFIG_PHY_GIGE
+#endif
+
 #endif /* __LS2_RDB_H */