void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
struct mxs_ssp_regs *ssp_regs;
- const uint32_t sspclk = mxs_get_sspclk(bus);
+ const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
+ const uint32_t sspclk = mxs_get_sspclk(clk);
uint32_t reg;
uint32_t divide, rate, tgtclk;
/*
* MXS DMA channels
*/
+#if defined(CONFIG_MX23)
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX28)
enum {
MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
- MXS_DMA_CHANNEL_AHB_APBH_SSP,
+ MXS_DMA_CHANNEL_AHB_APBH_HSADC,
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
+#endif
/*
* MXS DMA hardware command.
};
#endif
+static inline int mxs_ssp_bus_id_valid(int bus)
+{
+#if defined(CONFIG_MX23)
+ const unsigned int mxs_ssp_chan_count = 2;
+#elif defined(CONFIG_MX28)
+ const unsigned int mxs_ssp_chan_count = 4;
+#endif
+
+ if (bus >= mxs_ssp_chan_count)
+ return 0;
+
+ if (bus < 0)
+ return 0;
+
+ return 1;
+}
+
+static inline int mxs_ssp_clock_by_bus(unsigned int clock)
+{
+#if defined(CONFIG_MX23)
+ return 0;
+#elif defined(CONFIG_MX28)
+ return clock;
+#endif
+}
+
static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
{
switch (port) {
struct mxs_dma_desc *desc;
};
-#if defined(CONFIG_MX23)
-static const unsigned int mxsmmc_id_offset = 1;
-#elif defined(CONFIG_MX28)
-static const unsigned int mxsmmc_id_offset = 0;
-#endif
-
#define MXSMMC_MAX_TIMEOUT 10000
#define MXSMMC_SMALL_TRANSFER 512
priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
(data_count << MXS_DMA_DESC_BYTES_OFFSET);
- dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id + mxsmmc_id_offset;
+ dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
mxs_dma_desc_append(dmach, priv->desc);
if (mxs_dma_go(dmach)) {
bounce_buffer_stop(&bbstate);
struct mmc *mmc = NULL;
struct mxsmmc_priv *priv = NULL;
int ret;
-#if defined(CONFIG_MX23)
- const unsigned int mxsmmc_max_id = 2;
- const unsigned int mxsmmc_clk_id = 0;
-#elif defined(CONFIG_MX28)
- const unsigned int mxsmmc_max_id = 4;
- const unsigned int mxsmmc_clk_id = id;
-#endif
+ const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
- if (id >= mxsmmc_max_id)
+ if (!mxs_ssp_bus_id_valid(id))
return -ENODEV;
mmc = malloc(sizeof(struct mmc));
return -ENOMEM;
}
- ret = mxs_dma_init_channel(id + mxsmmc_id_offset);
+ ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
if (ret)
return ret;
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
/* MXS SPI: 4 ports and 3 chip selects maximum */
- if (bus > 3 || cs > 2)
+ if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
return 0;
else
return 1;
if (!mxs_slave)
return NULL;
- if (mxs_dma_init_channel(bus))
+ if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
goto err_init;
mxs_slave->slave.bus = bus;