powerpc/mpc85xx: add support for MMUv2 page sizes

e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4.  Add support for such pages.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index bb0dc1a653e193fb1f141e13ede0980f0c075198..fb674694e4363bdc14c8e73f0db377f8cb46843d 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -449,7 +449,7 @@ nexti:      mflr    r1              /* R1 = our PC */
 
        /* Set the size of the TLB to 4KB */
        mfspr   r3, MAS1
-       li      r2, 0xF00
+       li      r2, 0xF80
        andc    r3, r3, r2      /* Clear the TSIZE bits */
        ori     r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
        oris    r3, r3, MAS1_IPROT@h

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index f44fadcffd80599143faca65b6f38c278e34e097..23d33574a09d7a3779ee244cc1062d5891d5014c 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -66,7 +66,7 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
        _mas1 = mfspr(MAS1);
 
        *valid = (_mas1 & MAS1_VALID);
-       *tsize = (_mas1 >> 8) & 0xf;
+       *tsize = (_mas1 >> 7) & 0x1f;
        *epn = mfspr(MAS2) & MAS2_EPN;
        *rpn = mfspr(MAS3) & MAS3_RPN;
 #ifdef CONFIG_ENABLE_36BIT_PHYS
@@ -156,6 +156,13 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
        if (tlb == 1)
                use_tlb_cam(esel);
 
+       if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
+           tsize & 1) {
+               printf("%s: bad tsize %d on entry %d at 0x%08x\n",
+                       __func__, tsize, tlb, epn);
+               return;
+       }
+
        _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
        _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
        _mas2 = FSL_BOOKE_MAS2(epn, wimge);
@@ -251,7 +258,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
        unsigned int tlb_size;
        unsigned int wimge = MAS2_M;
        unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
-       unsigned int max_cam;
+       unsigned int max_cam, tsize_mask;
        u64 size, memsize = (u64)memsize_in_meg << 20;
 
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
@@ -261,15 +268,17 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
        if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
                /* Convert (4^max) kB to (2^max) bytes */
                max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+               tsize_mask = ~1U;
        } else {
                /* Convert (2^max) kB to (2^max) bytes */
                max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+               tsize_mask = ~0U;
        }
 
        for (i = 0; size && i < 8; i++) {
                int ram_tlb_index = find_free_tlbcam();
-               u32 camsize = __ilog2_u64(size) & ~1U;
-               u32 align = __ilog2(ram_tlb_address) & ~1U;
+               u32 camsize = __ilog2_u64(size) & tsize_mask;
+               u32 align = __ilog2(ram_tlb_address) & tsize_mask;
 
                if (ram_tlb_index == -1)
                        break;
@@ -281,7 +290,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
                if (camsize > max_cam)
                        camsize = max_cam;
 
-               tlb_size = (camsize - 10) / 2;
+               tlb_size = camsize - 10;
 
                set_tlb(1, ram_tlb_address, p_addr,
                        MAS3_SX|MAS3_SW|MAS3_SR, wimge,

diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 2e0e292da05df9e8ad8c14015478c1941b55c69d..b700a3a0bec55025a7067cfbaa0d65a89ca28c7a 100644 (file)
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -401,8 +401,8 @@ extern void print_bats(void);
 #define MAS1_IPROT     0x40000000
 #define MAS1_TID(x)    (((x) << 16) & 0x3FFF0000)
 #define MAS1_TS                0x00001000
-#define MAS1_TSIZE(x)  (((x) << 8) & 0x00000F00)
-#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10))
+#define MAS1_TSIZE(x)  (((x) << 7) & 0x00000F80)
+#define TSIZE_TO_BYTES(x) (1ULL << ((x) + 10))
 
 #define MAS2_EPN       0xFFFFF000
 #define MAS2_X0                0x00000040
@@ -458,22 +458,38 @@ extern void print_bats(void);
 #define FSL_BOOKE_MAS7(rpn) \
                (((u64)(rpn)) >> 32)
 
-#define BOOKE_PAGESZ_1K         0
-#define BOOKE_PAGESZ_4K         1
-#define BOOKE_PAGESZ_16K        2
-#define BOOKE_PAGESZ_64K        3
-#define BOOKE_PAGESZ_256K       4
-#define BOOKE_PAGESZ_1M         5
-#define BOOKE_PAGESZ_4M         6
-#define BOOKE_PAGESZ_16M        7
-#define BOOKE_PAGESZ_64M        8
-#define BOOKE_PAGESZ_256M       9
-#define BOOKE_PAGESZ_1G                10
-#define BOOKE_PAGESZ_4G                11
-#define BOOKE_PAGESZ_16GB      12
-#define BOOKE_PAGESZ_64GB      13
-#define BOOKE_PAGESZ_256GB     14
-#define BOOKE_PAGESZ_1TB       15
+#define BOOKE_PAGESZ_1K                0
+#define BOOKE_PAGESZ_2K                1
+#define BOOKE_PAGESZ_4K                2
+#define BOOKE_PAGESZ_8K                3
+#define BOOKE_PAGESZ_16K       4
+#define BOOKE_PAGESZ_32K       5
+#define BOOKE_PAGESZ_64K       6
+#define BOOKE_PAGESZ_128K      7
+#define BOOKE_PAGESZ_256K      8
+#define BOOKE_PAGESZ_512K      9
+#define BOOKE_PAGESZ_1M                10
+#define BOOKE_PAGESZ_2M                11
+#define BOOKE_PAGESZ_4M                12
+#define BOOKE_PAGESZ_8M                13
+#define BOOKE_PAGESZ_16M       14
+#define BOOKE_PAGESZ_32M       15
+#define BOOKE_PAGESZ_64M       16
+#define BOOKE_PAGESZ_128M      17
+#define BOOKE_PAGESZ_256M      18
+#define BOOKE_PAGESZ_512M      19
+#define BOOKE_PAGESZ_1G                20
+#define BOOKE_PAGESZ_2G                21
+#define BOOKE_PAGESZ_4G                22
+#define BOOKE_PAGESZ_8G                23
+#define BOOKE_PAGESZ_16GB      24
+#define BOOKE_PAGESZ_32GB      25
+#define BOOKE_PAGESZ_64GB      26
+#define BOOKE_PAGESZ_128GB     27
+#define BOOKE_PAGESZ_256GB     28
+#define BOOKE_PAGESZ_512GB     29
+#define BOOKE_PAGESZ_1TB       30
+#define BOOKE_PAGESZ_2TB       31
 
 #define TLBIVAX_ALL            4
 #define TLBIVAX_TLB0           0