board: ge: ppd: Enable CONFIG_DM_MMC
authorIan Ray <ian.ray@ge.com>
Thu, 31 Jan 2019 14:21:17 +0000 (16:21 +0200)
committerStefano Babic <sbabic@denx.de>
Sat, 13 Apr 2019 18:30:08 +0000 (20:30 +0200)
Use MMC device model, and remove USDHC pin configuration code since the
pinctrl driver is used.

Signed-off-by: Ian Ray <ian.ray@ge.com>
arch/arm/dts/imx53-ppd.dts
board/ge/mx53ppd/mx53ppd.c
configs/mx53ppd_defconfig
include/configs/mx53ppd.h

index 98e7dad0ba3a6fa78e3f46839cf8f735c8a286e9..f89d6f4672b9fb75117be57fa0d1a1fb1b6ab54f 100644 (file)
        model = "General Electric CS ONE";
        compatible = "ge,imx53-cpuvo", "fsl,imx53";
 };
+
+&iomuxc {
+       pinctrl-names = "default";
+
+       pinctrl_esdhc3: esdhc3grp {
+               fsl,pins = <
+                       MX53_PAD_PATA_DATA8__ESDHC3_DAT0        0x1d5
+                       MX53_PAD_PATA_DATA9__ESDHC3_DAT1        0x1d5
+                       MX53_PAD_PATA_DATA10__ESDHC3_DAT2       0x1d5
+                       MX53_PAD_PATA_DATA11__ESDHC3_DAT3       0x1d5
+                       MX53_PAD_PATA_DATA0__ESDHC3_DAT4        0x1d5
+                       MX53_PAD_PATA_DATA1__ESDHC3_DAT5        0x1d5
+                       MX53_PAD_PATA_DATA2__ESDHC3_DAT6        0x1d5
+                       MX53_PAD_PATA_DATA3__ESDHC3_DAT7        0x1d5
+                       MX53_PAD_PATA_RESET_B__ESDHC3_CMD       0x1d5
+                       MX53_PAD_PATA_IORDY__ESDHC3_CLK         0x1d5
+               >;
+       };
+};
+
+/* eMMC */
+&esdhc3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc3>;
+       compatible = "fsl,esdhc";
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
index 23bfe555417194791e3965f9763bf721beb1c8a9..9e13a2475558bd99e8f4b8936cbbeb9a2ab50cda 100644 (file)
@@ -122,79 +122,6 @@ static void setup_iomux_fec(void)
        imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
-       {MMC_SDHC3_BASE_ADDR},
-       {MMC_SDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-       return 1;
-}
-
-#define SD_CMD_PAD_CTRL                (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL            (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
-                                PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(bd_t *bis)
-{
-       static const iomux_v3_cfg_t sd1_pads[] = {
-               NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-                            SD_CMD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
-               MX53_PAD_EIM_DA11__GPIO3_11,
-       };
-
-       static const iomux_v3_cfg_t sd2_pads[] = {
-               NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
-               NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
-               MX53_PAD_EIM_DA13__GPIO3_13,
-       };
-
-       u32 index;
-       int ret;
-
-       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-       for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
-               switch (index) {
-               case 0:
-                       imx_iomux_v3_setup_multiple_pads(sd1_pads,
-                                                        ARRAY_SIZE(sd1_pads));
-                       break;
-               case 1:
-                       imx_iomux_v3_setup_multiple_pads(sd2_pads,
-                                                        ARRAY_SIZE(sd2_pads));
-                       break;
-               default:
-                       printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n",
-                              CONFIG_SYS_FSL_ESDHC_NUM);
-                       return -EINVAL;
-               }
-               ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-#endif
-
 #define I2C_PAD_CTRL   (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
                         PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 
index 04537c591a25e7aa6aa388297a15ae3d9f2550fb..ec3bc10f6d56338145d9b6e1a9778776359ef43f 100644 (file)
@@ -46,3 +46,7 @@ CONFIG_DM=y
 CONFIG_CMD_DM=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd"
+CONFIG_DM_MMC=y
+CONFIG_BLK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX5=y
index d2a8e6571af6ffea6cbe294ffc5e1268c4b9dd75..db6cd650f15022d6d59d31fe739d89d9c24728e0 100644 (file)
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
-#define CONFIG_SYS_FSL_ESDHC_NUM       2
-
 /* Eth Configs */
 
 #define CONFIG_FEC_MXC
        "image=/boot/fitImage\0" \
        "fdt_high=0xffffffff\0" \
        "dev=mmc\0" \
-       "devnum=0\0" \
+       "devnum=2\0" \
        "rootdev=mmcblk0p\0" \
        "quiet=quiet loglevel=0\0" \
        "console=" CONSOLE_DEV "\0" \