armv8: lx2160a: add icid setup for platform devices

Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index f00ef817b1f96e6233c0eafccb1e7774eb630ee4..e398aecd12ebb7f59f42c4309257fc3773769e7f 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -24,6 +24,7 @@ endif
 
 ifneq ($(CONFIG_ARCH_LX2160A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
+obj-y += icid.o lx2160_ids.o
 endif
 
 ifneq ($(CONFIG_ARCH_LS2080A),)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
new file mode 100644 (file)
index 0000000..3a0ed1f
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+
+struct icid_id_table icid_tbl[] = {
+       SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+       SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
+       SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+       SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+       SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID),
+       SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID),
+       SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID),
+       SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+       SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+       SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+       SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+       SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+       SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+       SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+       SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+       SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID),
+       SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c66fae43bfd5b58073e7e75f7f6e6e8718e537b0..03a40db186bd018d78da7e779b188b9fdeacd28d 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void)
 #endif
 
 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
-       defined(CONFIG_ARCH_LS2080A)
+       defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
        set_icids();
 #endif
 }

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 0e4bf331fd03601765ea00768f7b68e25e6c554b..d46477d96e269d2c08e9cbd4cf7354146bf8d2be 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -447,7 +447,9 @@ struct ccsr_gur {
        u8      res_538[0x550 - 0x538]; /* add more registers when needed */
        u32     sata1_amqr;
        u32     sata2_amqr;
-       u8      res_558[0x570-0x558];   /* add more registers when needed */
+       u32     sata3_amqr;
+       u32     sata4_amqr;
+       u8      res_560[0x570 - 0x560]; /* add more registers when needed */
        u32     misc1_amqr;
        u8      res_574[0x590-0x574];   /* add more registers when needed */
        u32     spare1_amqr;

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 93bdcc4caa7a451cc72b74ac614604dec3dbe3df..0b36416ad3637cfceff8d38a67e549a6dbaa44a9 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -108,5 +108,7 @@
 #define FSL_EDMA_STREAM_ID             70
 #define FSL_GPU_STREAM_ID              71
 #define FSL_DISPLAY_STREAM_ID          72
+#define FSL_SATA3_STREAM_ID            73
+#define FSL_SATA4_STREAM_ID            74
 
 #endif

diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index b509c0312e6ddad021bd25bf608a437c226c41fb..eff12747b411d061032c98535e381d8ff6f6d519 100644 (file)
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -27,6 +27,7 @@
 #include "../common/qixis.h"
 #include "../common/vid.h"
 #include <fsl_immap.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 
 #ifdef CONFIG_EMC2305
 #include "../common/emc2305.h"
@@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd)
        fdt_fsl_mc_fixup_iommu_map_entry(blob);
        fdt_fixup_board_enet(blob);
 #endif
+       fdt_fixup_icid(blob);
 
        return 0;
 }

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index be08a2b88b122e49fb724d00e24eeb00d51989b9..c0d2c7e8667921727be914d2cb42f29eba37240e 100644 (file)
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -93,8 +93,7 @@ typedef struct ccsr_sec {
        struct {
                u32     ms;     /* DECO LIODN Register, MS */
                u32     ls;     /* DECO LIODN Register, LS */
-       } decoliodnr[8];
-       u8      res4[0x40];
+       } decoliodnr[16];
        u32     dar;            /* DECO Avail Register */
        u32     drr;            /* DECO Reset Register */
        u8      res5[0x4d8];