LIB = lib$(BOARD).a
-OBJS = $(BOARD).o ../common/ar7240_flash.o ../common/ar7240_s26_phy.o ../common/common.o
-SOBJS = ../common/lowlevel_init.o
-
-ifeq ($(BOARD), ap121)
-SOBJS += hornet_pll_init.o
-endif
+OBJS = $(BOARD).o ../common/ar7240_flash.o ../common/ar7240_s26_phy.o ../common/common.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#include "ar7240_soc.h"
#if !defined(COMPRESSED_UBOOT)
-extern void hornet_ddr_init(void);
+extern void ar933x_ddr_init(void);
#endif
extern int ar7240_ddr_find_size(void);
-extern void hornet_ddr_tap_init(void);
+extern void ar933x_ddr_tap_init(void);
#define SETBITVAL(val, pos, bit) do {ulong bitval = (bit) ? 0x1 : 0x0; (val) = ((val) & ~(0x1 << (pos))) | ( (bitval) << (pos));} while(0)
{
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifndef COMPRESSED_UBOOT
- hornet_ddr_init();
+ ar933x_ddr_init();
#endif
/* Default tap values for starting the tap_init*/
all_led_off();
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- hornet_ddr_tap_init();
+ ar933x_ddr_tap_init();
#endif
// return memory size
+++ /dev/null
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
- .globl hornet_pll_init
- .text
- .align 4
-
-#define CLEAR_BIT(val, bit) ((val) & ~(1 << (bit)))
-#define SET_BIT(val, bit) ((val) | (1 << (bit)))
-
-#define CLEAR_PLL_POWER_DOWN(reg_val) CLEAR_BIT(reg_val, 30)
-#define SET_PLL_POWER_DOWN(reg_val) SET_BIT(reg_val, 30)
-#define SET_AHB_DIV_TO_4(reg_val) SET_BIT(SET_BIT(reg_val, 15), 16)
-#define CLEAR_PLL_BYPASS(reg_val) CLEAR_BIT(reg_val, 2)
-#define SET_PLL_BYPASS(reg_val) SET_BIT(reg_val, 2)
-
-/*
- * Helper macros.
- * These Clobber t7, t8 and t9
- * or t8, t8, t9;
- */
-#define set_reg(_reg, _val) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, _val; \
- sw t9, 0(t7);
-
-/* if reset button is active low -> use bne (branch on not equal) */
-#ifdef GPIO_RST_BUTTON_IS_ACTIVE_LOW
- #define recovery_jump(_branch) \
- bne t1, (1 << GPIO_RST_BUTTON_BIT), _branch;
-#else
- #define recovery_jump(_branch) \
- beq t1, (1 << GPIO_RST_BUTTON_BIT), _branch;
-#endif
-
-hornet_pll_init:
-
-#if 1
-/* These three wlan reset will avoid original issue,
- * so full chip reset isn't needed here.
- *
- * WLAN_RESET in RST_RESET (AR7240_RESET) register
- * 0x00C06B30 -> BIT(11) is set
- * 0x00C06330 -> BIT(11) is not set
- */
- set_reg(AR7240_RESET, 0x00C06B30)
- nop
- set_reg(AR7240_RESET, 0x00C06330)
- nop
- set_reg(AR7240_RESET, 0x00C06B30)
- nop
- set_reg(AR7240_RESET, 0x00C06330)
- nop
-
-reset_wlan:
- set_reg(AR7240_RESET, 0x00C06B30)
- nop
- set_reg(AR7240_RESET, 0x00C06330)
- nop
- li t5, 0x20
-
-check_val:
- beq zero, t5, reset_wlan
- addi t5, t5, -1
- li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS)
- lw t7, 0(t6)
- li t8, 0x10
- and t7, t7, t8
- bne zero, t7, check_val
- set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110E)
- nop
-#else
-/* clear wlan reset bit in RESET_Register 0x1c */
- set_reg(AR7240_RESET, 0x00C06B30)
- nop
- set_reg(AR7240_RESET, 0x00C06330)
- nop
-
-/* cleck bootstrap status, wait for bit4 on, then clear bit16 */
-wait_loop0:
- li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS)
- lw t7, 0(t6)
- li t8, 0x10
- and t7, t7, t8
- bne zero, t7, wait_loop0
- nop
- set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110E)
- nop
-#endif
-
-/* RTC reset */
-/* 0x1810704C -> RTC_FORCE_WAKE (RTC Force Wake) */
- set_reg(0x1810704C, 0x00000003)
- nop
- nop
-/* 0x18107040 -> RTC_RESET (RTC Reset and Force Sleep and Force Wakeup) */
- set_reg(0x18107040, 0x00000000)
- nop
- nop
- set_reg(0x18107040, 0x00000001)
- nop
-
-wait_loop1:
-/* 0x18107044 -> RTC_STATUS (RTC Sleep Status) */
- li t6, KSEG1ADDR(0x18107044)
- lw t7, 0(t6)
- li t8, 0x2
- and t7, t7, t8
- bne t8, t7, wait_loop1
- nop
-
-/*
- * AHB/APH reset
- * TODO: 0x18104000 is "Reset the Host Interface (HOST_INTF_RESET_CONTROL)" and bits 0:7 are RESERVED!
- */
-/*
- set_reg(0x18104000, 0x00000003)
- nop
- set_reg(0x18104000, 0x00000000)
- nop
-*/
-/*
- * MAC reset (TODO: ?? AR9344 has 0x18107000 register -> AR9344_RTC_BASE)
- */
-/*
- set_reg(0x18107000, 0x0000000F)
- nop
- set_reg(0x18107000, 0x00000000)
- nop
-*/
-
-#if 1 /* fetch pmu1.refv and ctrl2.tx from OTP */
- li t1, KSEG1ADDR(0x18114014)
- lw t2, 0(t1)
-
-otp_loop0:
- li t3, KSEG1ADDR(0x18115F18)
- lw t4, 0(t3)
- nop
- li t5, 0x7
- and t4, t4, t5
- li t5, 0x4
- bne t4, t5, otp_loop0
- nop
- li t6, KSEG1ADDR(0x18115F1C)
- lw t7, 0(t6)
- nop
- li t8, 0x80000080
- and t9, t7, t8
- beq t8, t9, fetch_otp
-
-otp_loop0_end:
- li t1, KSEG1ADDR(0x18114004)
- lw t2, 0(t1)
-
-otp_loop1:
- li t3, KSEG1ADDR(0x18115F18)
- lw t4, 0(t3)
- nop
- li t5, 0x7
- and t4, t4, t5
- li t5, 0x4
- bne t4, t5, otp_loop1
- nop
- li t6, KSEG1ADDR(0x18115F1C)
- lw t7, 0(t6)
- nop
- li t8, 0x80000080
- and t9, t7, t8
-
-default_pmu:
- li t5, 0x80 /* default 0x031c4386 */
- bne t8, t9, otp_end
-
-fetch_otp:
- srl t8, t7, 0x18
- li t1, 0xf
- and t2, t1, t7 /* USB */
- and t5, t1, t8 /* PMU */
-
-check_pmu:
- li t0, 0x4 /* PMU range should be 0x4~0xa */
- bgt t0, t5, default_pmu
- nop
- li t0, 0xa /* PMU range should be 0x4~0xa */
- blt t0, t5, default_pmu
- nop
- li t0, 0x4
- sll t5, t5, t0
-
-otp_end:
-#endif
-
-#if 1 /* Program PMU */
-#define PMU_TEST_NO 1000
- li t6, KSEG1ADDR(0x18116C40)
- li t9, 0xbd000010
- li t0, 0
- li t1, 0
- li t2, 0
- li t3, PMU_TEST_NO
- sw t3, 12(t9)
-
-pmu_loop0:
- beq zero, t3, pmu_loop0_end
- nop
- addi t3, t3, -1
- li t7, 0x10180000 /* ldo_tune 0x3 */
- nop
- sw t7, 4(t6)
- nop
- lw t8, 4(t6)
- nop
- beq t8, t7, pmu_loop0_end
- nop
- addiu t0, t0, 1
- b pmu_loop0
- nop
-
-pmu_loop0_end:
- li t3, PMU_TEST_NO
-
-pmu_loop1:
- beq zero, t3, pmu_loop1_end
- nop
- addi t3, t3, -1
- //li t7, 0x031c4326 /* 1.100V */
- //li t7, 0x031c4336 /* 1.125V */
- //li t7, 0x031c4346 /* 1.150V */
- //li t7, 0x031c4356 /* 1.175V */
- //li t7, 0x031c4366 /* 1.200V */
- //li t7, 0x031c4376 /* 1.225V */
- li t7, 0x031c4386 /* 1.250V (DEFAULT) */
- //li t7, 0x031c4396 /* 1.275V */
- //li t7, 0x031c43a6 /* 1.300V */
- nop
-
-#if 1 /* from OTP */
- li t8, 0xFFFFFF0F
- and t7, t7, t8
- or t7, t7, t5
-#endif
- sw t7, 0(t6)
- nop
- lw t8, 0(t6)
- nop
- beq t8, t7, pmu_loop1_end
- nop
- addiu t1, t1, 1
- b pmu_loop1
- nop
-
-pmu_loop1_end:
- li t3, PMU_TEST_NO
-
-pmu_loop2:
- beq zero, t3, pmu_loop2_end
- nop
- addi t3, t3, -1
- li t7, 0x10380000 /* ldo_tune 0x3 */
- nop
- sw t7, 4(t6)
- nop
- lw t8, 4(t6)
- nop
- beq t8, t7, pmu_loop2_end
- nop
- addiu t2, t2, 1
- b pmu_loop2
- nop
-
-pmu_loop2_end:
- sw t0, 0(t9)
- nop
- sw t1, 4(t9)
- nop
- sw t2, 8(t9)
- nop
-#endif
-
-#if 1 /* Program ki, kd */
-// TODO: ??
-/* Program ki/kd */
-#if CONFIG_40MHZ_XTAL_SUPPORT
- set_reg(0x18116244, 0x19e82f01)
-#else
- set_reg(0x18116244, 0x18e82f01)
-#endif
- nop
-
-/* Program phase shift */
- li t6, KSEG1ADDR(0x18116248)
- lw t7, 0(t6)
- li t8, 0xc07fffff
- and t7, t7, t8
- li t8, 0x800000
- or t7, t7, t8
- sw t7, 0(t6)
- nop
-#endif
-
-/* max AHB Master wait time out ... */
- set_reg(0x1800009C, 0xfffff)
- nop
-
-/*
- * O/C recovery mode
- *
- * If RESET BUTTON is pressed and hold during power on
- * we will use default PLL and clocks configuration (400/400/200)
- *
- * Using t0 and t1 (t1 indicates if recovery mode was turned on)
- */
-pll_clock_control_oc_recovery:
- li t0, KSEG1ADDR(AR7240_GPIO_IN)
- lw t1, 0(t0)
- and t1, t1, (1 << GPIO_RST_BUTTON_BIT)
- recovery_jump(pll_clock_control_default)
- nop
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-/*
- * PLL and CLOCK configuration from FLASH
- *
- * Using t0, t2 and t3 (t2 stores magic value from flash)
- */
-pll_clock_control_flash:
- li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
- lw t2, 0(t0) // load PLL_IN_FLASH_MAGIC value from FLASH
- bne t2, PLL_IN_FLASH_MAGIC, pll_clock_control // jump if we don't have PLL_MAGIC value in FLASH
- nop
- lw t3, 8(t0) // load CLOCK_CONTROL register value from FLASH
- or t3, t3, 0x18004 // set BYPASS bit and make AHB_POST_DIV = 4
- li t0, KSEG1ADDR(AR7240_CPU_CLOCK_CONTROL) // load CLOCK_CONTROL register address
- sw t3, 0(t0) // store value in CLOCK_CONTROL register
- j pll_settle_time // jump to pll_settle_time
- nop
-#endif
-
-pll_clock_control:
-/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */
-/* in some cases, the SoC doesn't start with higher clock on AHB */
- set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(SET_PLL_BYPASS(CPU_CLK_CONTROL_VAL)))
- j pll_settle_time
- nop
-
-pll_clock_control_default:
-/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */
-/* in some cases, the SoC doesn't start with higher clock on AHB */
- set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(SET_PLL_BYPASS(CPU_CLK_CONTROL_VAL_DEFAULT)))
- nop
-
-pll_settle_time:
-/* set SETTLE_TIME in CPU PLL */
- set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL)
- nop
-
-pll_unlock_handler_oc_recovery:
- recovery_jump(pll_unlock_handler_default)
- nop
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-pll_unlock_handler_flash:
- bne t2, PLL_IN_FLASH_MAGIC, pll_unlock_handler // jump if we don't have PLL_MAGIC value in FLASH
- nop
- li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
- lw t3, 4(t0) // load CPU_PLL_CONFIG register value from FLASH
- or t3, t3, 0x40000000 // set CPU_PLLPWD bit (power down for CPU PLL)
- li t0, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) // load CPU_PLL_CONFIG register address
- sw t3, 0(t0) // store value in CPU_PLL_CONFIG register
- j wait_loop2 // jump to wait_loop2
- nop
-#endif
-
-pll_unlock_handler:
-/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
- set_reg(AR7240_CPU_PLL_CONFIG, SET_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL))
- j wait_loop2
- nop
-
-pll_unlock_handler_default:
-/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
- set_reg(AR7240_CPU_PLL_CONFIG, SET_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL_DEFAULT))
- nop
-
-wait_loop2:
- li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
- lw t7, 0(t6)
- li t8, 0x80000000
- and t7, t7, t8
- bne zero, t7, wait_loop2
- nop
-
-/* put frac bit19:10 configuration */
-/* TODO: do we need this? */
- set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL)
- nop
-
-pll_lock_handler_oc_recovery:
- recovery_jump(pll_lock_handler_default)
- nop
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-pll_lock_handler_flash:
- bne t2, PLL_IN_FLASH_MAGIC, pll_lock_handler // jump if we don't have PLL_MAGIC value in FLASH
- nop
- li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
- lw t3, 4(t0) // load CPU_PLL_CONFIG register value from FLASH
- li t0, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) // load CPU_PLL_CONFIG register address
- sw t3, 0(t0) // store value in CPU_PLL_CONFIG register
- j wait_loop3 // jump to wait_loop3
- nop
-#endif
-
-pll_lock_handler:
-/* clear PLL power down bit in CPU PLL configuration */
- set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL)
- j wait_loop3
- nop
-
-pll_lock_handler_default:
-/* clear PLL power down bit in CPU PLL configuration */
- set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL_DEFAULT)
- nop
-
-wait_loop3:
-/* wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
- li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
- lw t7, 0(t6)
- li t8, 0x80000000
- and t7, t7, t8
- bne zero, t7, wait_loop3
- nop
-
-/* confirm DDR PLL lock */
- li t3, 100
- li t4, 0
-
-start_meas0:
- addi t4, t4, 1
- bgt t4, t3, pll_unlock_handler_oc_recovery
- nop
- li t5, 5
-
-start_meas:
- li t6, KSEG1ADDR(0x18116248)
- lw t7, 0(t6)
- li t8, 0xBFFFFFFF
- and t7, t7, t8
- sw t7, 0(t6)
- nop
-
-/* delay */
- li t9, 10
-
-delayloop0:
- subu t9, t9, 1
- bne t9, zero, delayloop0
- nop
- li t8, 0x40000000
- or t7, t7, t8
- sw t7, 0(t6)
- nop
-
-meas_done_statue:
- li t6, KSEG1ADDR(0x1811624C)
- lw t7, 0(t6)
- li t8, 0x8
- and t7, t7, t8
- beq zero, t7, meas_done_statue
- nop
-
-meas_result:
- li t6, KSEG1ADDR(0x18116248)
- lw t7, 0(t6)
- li t8, 0x007FFFF8
- and t7, t7, t8
- srl t7, t7, 3
- li t8, 0x4000
- bgt t7, t8, start_meas0
- nop
- addi t5, t5, -1
- bne zero, t5, start_meas
- nop
-
-pll_clear_bypass_oc_recovery:
- recovery_jump(pll_clear_bypass_default)
- nop
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-pll_clear_bypass_flash:
- bne t2, PLL_IN_FLASH_MAGIC, pll_clear_bypass // jump if we don't have PLL_MAGIC value in FLASH
- nop
- li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
- lw t3, 8(t0) // load CLOCK_CONTROL register value from FLASH
- li t0, KSEG1ADDR(AR7240_CPU_CLOCK_CONTROL) // load CLOCK_CONTROL register address
- sw t3, 0(t0) // store value in CLOCK_CONTROL register
- j end // jump to end
- nop
-#endif
-
-pll_clear_bypass:
-/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
- set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL)
- j end
- nop
-
-pll_clear_bypass_default:
-/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
- set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL_DEFAULT)
- nop
-
-/* Sync mode, Set Bit 8 of DDR Tap Conrtol 3 register */
-/*
- * TODO: something is wrong here?
- * There is no AR7240_DDR_TAP_CONTROL3 in AR9331 datasheet!
- */
-/*
- set_reg(AR7240_DDR_TAP_CONTROL3, 0x10105);
- nop
-*/
-
-end:
- jr ra
- nop
+++ /dev/null
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
-/*
- * Helper macros.
- * These Clobber t7, t8 and t9
- */
-#define clear_mask(_reg, _mask) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, ~_mask; \
- and t8, t8, t9; \
- sw t8, 0(t7)
-
-#define set_val(_reg, _mask, _val) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, ~_mask; \
- and t8, t8, t9; \
- li t9, _val; \
- or t8, t8, t9; \
- sw t8, 0(t7)
-
-#define set_val_f(_reg, _mask, _val) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, ~_mask; \
- and t8, t8, t9; \
- li t6, KSEG1ADDR(_val); \
- lw t9, 0(t6); \
- or t8, t8, t9; \
- sw t8, 0(t7)
-
-
-#define get_val(_reg, _mask, _shift, _res_reg) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, _mask; \
- and t8, t8, t9; \
- srl _res_reg, t8, _shift \
-
-#define pll_clr(_mask) \
- clear_mask(AR7240_CPU_PLL_CONFIG, _mask)
-
-#define pll_set(_mask, _val) \
- set_val(AR7240_CPU_PLL_CONFIG, _mask, _val)
-
-#define pll_set_f(_mask, _val) \
- set_val_f(AR7240_CPU_PLL_CONFIG, _mask, _val)
-
-#define pll_get(_mask, _shift, _res_reg) \
- get_val(AR7240_CPU_PLL_CONFIG, _mask, _shift, _res_reg)
-
-#define clk_clr(_mask) \
- clear_mask(AR7240_CPU_CLOCK_CONTROL, _mask)
-
-#define clk_set(_mask, _val) \
- set_val(AR7240_CPU_CLOCK_CONTROL, _mask, _val)
-
-#define clk_get(_mask, _shift, _res_reg) \
- get_val(AR7240_CPU_CLOCK_CONTROL, _mask, _shift, _res_reg)
-
-
-/******************************************************************************
- * first level initialization:
- *
- * 0) If clock cntrl reset switch is already set, we're recovering from
- * "divider reset"; goto 3.
- * 1) Setup divide ratios.
- * 2) Reset.
- * 3) Setup pll's, wait for lock.
- *
- *****************************************************************************/
-
-.globl lowlevel_init
-
-lowlevel_init:
- /*
- * The code below is for the real chip. Wont work on FPGA
- */
-
- b hornet_pll_init
- jr ra
- nop
-
--- /dev/null
+/*
+ * Startup Code for MIPS32 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <ar7240_soc.h>
+
+ .globl ar933x_ddr_init
+ .text
+ .align 4
+
+#define set_mem(_mem, _val) \
+ li t9, _mem; \
+ sw _val, 0(t9);
+
+//============================================
+// init DDR1 parameter before rel_start
+//===========================================
+ar933x_ddr_init:
+ // 0x18000000 (DDR_CONFIG, p. 54)
+ // CFG_DDR_CONFIG_VAL = 0x7fbc8cd0 (ap121.h)
+ li t8, CFG_DDR_CONFIG_VAL;
+ set_mem(0xB8000000, t8);
+
+ // 0x18000004 (DDR_CONFIG2, p. 55)
+ // CFG_DDR_CONFIG2_VAL = 0x99d0e6a8 (ap121.h)
+ li t8, CFG_DDR_CONFIG2_VAL;
+ set_mem(0xB8000004, t8);
+
+/*
+ * WR720N v3 (CH version) has wrong bootstrap configuration,
+ * so the memory type cannot be recognized automatically
+ */
+#if !defined(CONFIG_FOR_TPLINK_WR720N_V3)
+mem_type:
+ // TODO: what about SDRAM?
+ // 0x180600AC (BOOT_STRAP, p. 81)
+ li t8, 0xB80600AC // load BOOT_STRAP reg address
+ lw t9, 0(t8) // and its value
+ li t8, 0x2000 // 0x2000 -> BIT13 is set
+ and t9, t9, t8
+ beq t9, zero, ddr1_config // jump if we have DDR1
+
+ddr2_config:
+ // Enable DDR2
+ // 0x1800008C (DDR_DDR2_CONFIG, p. 58)
+ li t8, 0xA59;
+ set_mem(0xB800008C, t8);
+
+ // Precharge All
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x8;
+ set_mem(0xB8000010, t8);
+
+ // Disable High Temperature Self-Refresh Rate
+ // 0x18000090 (DDR_EMR2, p. 58)
+ li t8, 0x0;
+ set_mem(0xB8000090, t8);
+
+ // Extended Mode Register 2 Set (EMR2S)
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x10;
+ set_mem(0xB8000010, t8);
+
+ // 0x18000094 (DDR_EMR3, p. 58)
+ li t8, 0x0;
+ set_mem(0xB8000094, t8);
+
+ // Extended Mode Register 3 Set (EMR3S)
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x20;
+ set_mem(0xB8000010, t8);
+
+ // Enable DLL
+ // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
+ li t8, 0x0;
+ set_mem(0xB800000C, t8);
+
+ // Extended Mode Register Set (EMRS)
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x2;
+ set_mem(0xB8000010, t8);
+
+ // Reset DLL
+ // 0x18000008 (DDR_MODE_REGISTER, p. 55)
+ li t8, 0x100;
+ set_mem(0xB8000008, t8);
+
+ // Mode Register Set (MRS)
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x1;
+ set_mem(0xB8000010, t8);
+
+ // Precharge All
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x8;
+ set_mem(0xB8000010, t8);
+
+ // Auto Refresh
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x4;
+ set_mem(0xB8000010, t8);
+
+ // Auto Refresh
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x4;
+ set_mem(0xB8000010, t8);
+
+ // Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8
+ // 0x18000008 (DDR_MODE_REGISTER, p. 55)
+ li t8, 0xa33;
+ set_mem(0xB8000008, t8);
+
+ // Mode Register Set (MRS)
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x1;
+ set_mem(0xB8000010, t8);
+
+ // E7,E8,E9 equal to 1(Enable OCD defaults), Enable DLL, Reduced Drive Strength
+ // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
+ li t8, 0x382;
+ set_mem(0xB800000C, t8);
+
+ // Extended Mode Register Set (EMRS)
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x2;
+ set_mem(0xB8000010, t8);
+
+ // E7,E8,E9 equal to 0(OCD exit), Enable DLL, Reduced Drive Strength
+ // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
+ li t8, 0x402;
+ set_mem(0xB800000C, t8);
+
+ // Extended Mode Register Set (EMRS)
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x2;
+ set_mem(0xB8000010, t8);
+
+ // Refresh control. Bit 14 is enable. Bits<13:0> Refresh time
+ // 0x18000014 (DDR_REFRESH, p. 56)
+ li t8, CFG_DDR_REFRESH_VAL;
+ set_mem(0xB8000014, t8);
+
+ // DQS 0 Tap Control (needs tuning)
+ // 0x1800001C (TAP_CONTROL_0, p. 56)
+ li t8, CFG_DDR_TAP0_VAL;
+ set_mem(0xB800001C, t8);
+
+ // DQS 1 Tap Control (needs tuning)
+ // 0x18000020 (TAP_CONTROL_1, p. 57)
+ li t8, CFG_DDR_TAP1_VAL;
+ set_mem(0xB8000020, t8);
+
+ // For 16-bit DDR
+ // 0x18000018 (DDR_RD_DATA_THIS_CYCLE, p. 56)
+ li t8, 0x00ff;
+ set_mem(0xB8000018, t8);
+
+ nop
+ jr ra
+#endif /* !defined(CONFIG_FOR_TPLINK_WR720N_V3) */
+
+ddr1_config:
+ // Precharge All
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x8;
+ set_mem(0xB8000010, t8);
+
+ // 0x18000008 (DDR_MODE_REGISTER, p. 55)
+ li t8, CFG_DDR_MODE_VAL_INIT;
+ set_mem(0xB8000008, t8);
+
+ // Write Mode Word in DDR
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x1;
+ set_mem(0xB8000010, t8);
+
+ // Enable DLL, High drive strength from DDR
+ // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
+ li t8, 0x2;
+ set_mem(0xB800000C, t8);
+
+ // Write Extended Mode Word of DDR
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x2;
+ set_mem(0xB8000010, t8);
+
+ // Precharge All
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x8;
+ set_mem(0xB8000010, t8);
+
+ // DLL out of reset, CAS Latency 3
+ // 0x18000008 (DDR_MODE_REGISTER, p. 55)
+ li t8, CFG_DDR_MODE_VAL;
+ set_mem(0xB8000008, t8);
+
+ // Write mode word
+ // 0x18000010 (DDR_CONTROL, p. 56)
+ li t8, 0x1;
+ set_mem(0xB8000010, t8);
+
+ // Refresh control. Bit 14 is enable. Bits<13:0> Refresh time
+ // 0x18000014 (DDR_REFRESH, p. 56)
+ li t8, CFG_DDR_REFRESH_VAL;
+ set_mem(0xB8000014, t8);
+
+ // DQS 0 Tap Control (needs tuning)
+ // 0x1800001C (TAP_CONTROL_0, p. 56)
+ li t8, CFG_DDR_TAP0_VAL;
+ set_mem(0xB800001C, t8);
+
+ // DQS 1 Tap Control (needs tuning)
+ // 0x18000020 (TAP_CONTROL_1, p. 57)
+ li t8, CFG_DDR_TAP1_VAL;
+ set_mem(0xB8000020, t8);
+
+ // For 16-bit DDR
+ // 0x18000018 (DDR_RD_DATA_THIS_CYCLE, p. 56)
+ li t8, 0x00ff;
+ set_mem(0xB8000018, t8);
+
+ nop
+ jr ra
+
+/*
+ * void ar933x_ddr_tap_init(void)
+ *
+ * This "function" is used to find the tap settings for the DDR
+ */
+ .globl ar933x_ddr_tap_init
+ .ent ar933x_ddr_tap_init
+ar933x_ddr_tap_init: /* { */
+
+ li t1,0x80500000
+ li t0,0xffffffff
+
+ sw t0,0x0(t1)
+ sw t0,0x4(t1)
+ sw t0,0x8(t1)
+ sw t0,0xc(t1)
+
+ nop
+ nop
+
+ddr_pat_init:
+ li t8, 0xa0002000
+ li t0, 0x00
+ li t1, 0x100
+
+write_loop_start:
+ andi t2, t0, 0x03
+
+pat_000:
+ li t3, 0x00
+ bne t2, t3,pat_001
+ li t9, 0x00000000
+ sw t9, 0x0 (t8)
+ b pat_004
+
+pat_001:
+ li t3, 0x01
+ bne t2, t3,pat_002
+ li t9, 0x0000ffff
+ sw t9, 0x0 (t8)
+ b pat_004
+
+pat_002:
+ li t3, 0x02
+ bne t2, t3,pat_003
+ li t9, 0xffff0000
+ sw t9, 0x0 (t8)
+ b pat_004
+
+pat_003:
+ li t3, 0x03
+ bne t2, t3,pat_004
+ li t9, 0xffffffff
+ sw t9, 0x0 (t8)
+
+pat_004:
+ andi t2, t0, 0x0c
+ li t3, 0x00
+ bne t2, t3,pat_005
+ li t9, 0x00000000
+ sw t9, 0x4 (t8)
+ b pat_008
+
+pat_005:
+ li t3, 0x04
+ bne t2, t3,pat_006
+ li t9, 0x0000ffff
+ sw t9, 0x4 (t8)
+ b pat_008
+
+pat_006:
+ li t3, 0x08
+ bne t2, t3,pat_007
+ li t9, 0xffff0000
+ sw t9, 0x4 (t8)
+ b pat_008
+
+pat_007:
+ li t3, 0x0c
+ bne t2, t3,pat_008
+ li t9, 0xffffffff
+ sw t9, 0x4 (t8)
+
+pat_008:
+ andi t2, t0, 0x30
+ li t3, 0x00
+ bne t2, t3,pat_009
+ li t9, 0x00000000
+ sw t9, 0x8 (t8)
+ b pat_00c
+
+pat_009:
+ li t3, 0x10
+ bne t2, t3,pat_00a
+ li t9, 0x0000ffff
+ sw t9, 0x8 (t8)
+ b pat_00c
+
+pat_00a:
+ li t3, 0x20
+ bne t2, t3,pat_00b
+ li t9, 0xffff0000
+ sw t9, 0x8 (t8)
+ b pat_00c
+
+pat_00b:
+ li t3, 0x30
+ bne t2, t3,pat_00c
+ li t9, 0xffffffff
+ sw t9, 0x8 (t8)
+
+pat_00c:
+ andi t2, t0, 0xc0
+ li t3, 0x00
+ bne t2, t3,pat_00d
+ li t9, 0x00000000
+ sw t9, 0xc (t8)
+ b pat_done
+
+pat_00d:
+ li t3, 0x40
+ bne t2, t3,pat_00e
+ li t9, 0x0000ffff
+ sw t9, 0xc (t8)
+ b pat_done
+
+pat_00e:
+ li t3, 0x80
+ bne t2, t3,pat_00f
+ li t9, 0xffff0000
+ sw t9, 0xc (t8)
+ b pat_done
+
+pat_00f:
+ li t3, 0xc0
+ bne t2, t3,pat_done
+ li t9, 0xffffffff
+ sw t9, 0xc (t8)
+
+pat_done:
+ addiu t0, t0, 0x1
+ addiu t8, t8, 0x10
+ bne t0, t1, write_loop_start
+
+###### ddr init over #########
+
+ li a0, 0xa0002000
+ li a1, 0x80002000 ### Start address of the pattern 200
+ li a2, 0x80003000 ### End Address of the pattern 220
+ li t0, 0xb800001c ## Tap settings addr
+ lw a3, 0x0(t0) ## loading default tap value
+ nop
+ ori t0, a3, 0x0
+ nop
+ li t1, 0x1 ## $t1=1 indicates increasing tap value, 0 = decreasing
+
+load_tap:
+ li t7, 0x2
+ #li t7, 0x200 ## No. of times read has to happen for 1 tap setting
+ li t8, 0xb8000000 #### Loading Tap Setting
+ sw t0, 0x1c(t8)
+ nop
+ sw t0, 0x20(t8)
+ nop
+ #if 0 /* Hornet doesn't have DQS2, DQS3*/
+ sw t0, 0x24(t8)
+ nop
+ sw t0, 0x28(t8)
+ nop
+ #endif
+
+###### t0 stores current tap setting under test
+###### t1 indicates increment or decrement of tap
+
+pat_read:
+ ori t2, a0, 0x0
+ nop
+ ori t3, a1, 0x0
+ nop
+ ori t4, a2, 0x0
+ nop
+
+tap_addr_loop:
+ lw t5, 0x0(t2)
+ nop
+ lw t6, 0x0(t3)
+ nop
+ nop
+
+ bne t5, t6, tap_fail # jump to fail if not equal
+ nop
+ nop
+ nop
+
+ addiu t2, t2, 0x4 #incrementing addr
+ addiu t3, t3, 0x4
+ nop
+ nop
+
+ bne t3, t4, tap_addr_loop # compare new addr if end addr not reached
+ nop
+
+ addiu t7, t7, -1 # read passed for all locations once hence decrement t7
+ nop
+ bnez t7, pat_read # t7 = 0 represents passing of all locations for given tap
+ nop
+ nop
+
+ bnez t1, tap_incr # increment tap if t1 = 1
+ nop
+ nop
+
+ bnez t0, tap_decr ## $t0=0 implies tap=0 works
+ nop ## so low limit=0, else decrement tap value
+ nop
+ li t8, 0x80500000 ## assigning lower limit = 0
+ sw t0, 0x0(t8)
+ add t9, t9, t0 ##adding lower limit to upper limit (used to calc mid value)
+ nop
+ nop
+
+ b tap_calc
+ nop
+ nop
+
+tap_decr: # decrement t0 by 1 and move to loading this new tap
+ addiu t0, t0 , -1
+ nop
+ b load_tap
+ nop
+ nop
+
+tap_incr:
+ addiu t0, t0 , 0x1
+ nop
+ xori v1, t0, 0x20 # limiting upper limit to 0x20
+ nop
+ bnez v1, load_tap
+ nop
+ nop
+ b up_limit
+ nop
+ nop
+
+tap_fail:
+ bnez t1, up_limit # t1=0 means lower limit detected @ fail else upper limit
+ nop
+ nop
+ nop
+ addiu t0, t0, 0x1
+ nop
+ li t8, 0x80500000 # storing lower limit
+ nop
+ sw t0, 0x0(t8)
+ add t9, t9, t0 # storing lower limit# adding lower limit and upper limit
+ nop
+ nop
+ nop
+
+ b tap_calc
+ nop
+ nop
+
+up_limit:
+ addiu t0, t0, -1
+ li t1, 0x0 ## changing to decreasing tap mode
+ li t8, 0x80500000 ## storing upper limit
+ sw t0, 0x4(t8)
+ ori t9, t0, 0x0
+ nop
+ nop
+ nop
+
+ ori t0, a3, 0x0 # loading default tap value
+ nop
+ b load_tap
+ nop
+ nop
+
+tap_calc: ## calculating mid value of the tap, storing DQS0, DQS1 in 0x80500008, 0x8050000c resp.
+ li t7, 0x2
+ nop
+ div t9, t7
+ nop
+ mfhi t6
+ mflo t5
+ nop
+ nop
+ add t6, t6, t5
+ li t8, 0x80500000
+ nop
+ sw t5, 0x8(t8)
+ nop
+ sw t6, 0xc(t8)
+ nop
+ nop
+ li t8, 0xb8000000 #### Loading Tap Setting
+ nop
+ sw t5, 0x1c(t8)
+ nop
+ sw t6, 0x20(t8)
+ nop
+ nop
+ nop
+
+end:
+ nop
+ nop
+ nop
+ jr ra
+
+ .end ar933x_ddr_tap_init
+/* } */
--- /dev/null
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <ar7240_soc.h>
+
+ .globl lowlevel_init
+ .type lowlevel_init, @function
+ .text
+ .align 4
+
+#define CLEAR_BIT(val, bit) ((val) & ~(1 << (bit)))
+#define SET_BIT(val, bit) ((val) | (1 << (bit)))
+
+#define CLEAR_PLL_POWER_DOWN(reg_val) CLEAR_BIT(reg_val, 30)
+#define SET_PLL_POWER_DOWN(reg_val) SET_BIT(reg_val, 30)
+#define SET_AHB_DIV_TO_4(reg_val) SET_BIT(SET_BIT(reg_val, 15), 16)
+#define CLEAR_PLL_BYPASS(reg_val) CLEAR_BIT(reg_val, 2)
+#define SET_PLL_BYPASS(reg_val) SET_BIT(reg_val, 2)
+
+/*
+ * Helper macros.
+ * These Clobber t7, t8 and t9
+ * or t8, t8, t9;
+ */
+#define set_reg(_reg, _val) \
+ li t7, KSEG1ADDR(_reg); \
+ lw t8, 0(t7); \
+ li t9, _val; \
+ sw t9, 0(t7);
+
+/* if reset button is active low -> use bne (branch on not equal) */
+#ifdef GPIO_RST_BUTTON_IS_ACTIVE_LOW
+ #define recovery_jump(_branch) \
+ bne t1, (1 << GPIO_RST_BUTTON_BIT), _branch;
+#else
+ #define recovery_jump(_branch) \
+ beq t1, (1 << GPIO_RST_BUTTON_BIT), _branch;
+#endif
+
+lowlevel_init:
+
+#if 1
+/* These three wlan reset will avoid original issue,
+ * so full chip reset isn't needed here.
+ *
+ * WLAN_RESET in RST_RESET (AR7240_RESET) register
+ * 0x00C06B30 -> BIT(11) is set
+ * 0x00C06330 -> BIT(11) is not set
+ */
+ set_reg(AR7240_RESET, 0x00C06B30)
+ nop
+ set_reg(AR7240_RESET, 0x00C06330)
+ nop
+ set_reg(AR7240_RESET, 0x00C06B30)
+ nop
+ set_reg(AR7240_RESET, 0x00C06330)
+ nop
+
+reset_wlan:
+ set_reg(AR7240_RESET, 0x00C06B30)
+ nop
+ set_reg(AR7240_RESET, 0x00C06330)
+ nop
+ li t5, 0x20
+
+check_val:
+ beq zero, t5, reset_wlan
+ addi t5, t5, -1
+ li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS)
+ lw t7, 0(t6)
+ li t8, 0x10
+ and t7, t7, t8
+ bne zero, t7, check_val
+ set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110E)
+ nop
+#else
+/* clear wlan reset bit in RESET_Register 0x1c */
+ set_reg(AR7240_RESET, 0x00C06B30)
+ nop
+ set_reg(AR7240_RESET, 0x00C06330)
+ nop
+
+/* cleck bootstrap status, wait for bit4 on, then clear bit16 */
+wait_loop0:
+ li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS)
+ lw t7, 0(t6)
+ li t8, 0x10
+ and t7, t7, t8
+ bne zero, t7, wait_loop0
+ nop
+ set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110E)
+ nop
+#endif
+
+/* RTC reset */
+/* 0x1810704C -> RTC_FORCE_WAKE (RTC Force Wake) */
+ set_reg(0x1810704C, 0x00000003)
+ nop
+ nop
+/* 0x18107040 -> RTC_RESET (RTC Reset and Force Sleep and Force Wakeup) */
+ set_reg(0x18107040, 0x00000000)
+ nop
+ nop
+ set_reg(0x18107040, 0x00000001)
+ nop
+
+wait_loop1:
+/* 0x18107044 -> RTC_STATUS (RTC Sleep Status) */
+ li t6, KSEG1ADDR(0x18107044)
+ lw t7, 0(t6)
+ li t8, 0x2
+ and t7, t7, t8
+ bne t8, t7, wait_loop1
+ nop
+
+/*
+ * AHB/APH reset
+ * TODO: 0x18104000 is "Reset the Host Interface (HOST_INTF_RESET_CONTROL)" and bits 0:7 are RESERVED!
+ */
+/*
+ set_reg(0x18104000, 0x00000003)
+ nop
+ set_reg(0x18104000, 0x00000000)
+ nop
+*/
+/*
+ * MAC reset (TODO: ?? AR9344 has 0x18107000 register -> AR9344_RTC_BASE)
+ */
+/*
+ set_reg(0x18107000, 0x0000000F)
+ nop
+ set_reg(0x18107000, 0x00000000)
+ nop
+*/
+
+#if 1 /* fetch pmu1.refv and ctrl2.tx from OTP */
+ li t1, KSEG1ADDR(0x18114014)
+ lw t2, 0(t1)
+
+otp_loop0:
+ li t3, KSEG1ADDR(0x18115F18)
+ lw t4, 0(t3)
+ nop
+ li t5, 0x7
+ and t4, t4, t5
+ li t5, 0x4
+ bne t4, t5, otp_loop0
+ nop
+ li t6, KSEG1ADDR(0x18115F1C)
+ lw t7, 0(t6)
+ nop
+ li t8, 0x80000080
+ and t9, t7, t8
+ beq t8, t9, fetch_otp
+
+otp_loop0_end:
+ li t1, KSEG1ADDR(0x18114004)
+ lw t2, 0(t1)
+
+otp_loop1:
+ li t3, KSEG1ADDR(0x18115F18)
+ lw t4, 0(t3)
+ nop
+ li t5, 0x7
+ and t4, t4, t5
+ li t5, 0x4
+ bne t4, t5, otp_loop1
+ nop
+ li t6, KSEG1ADDR(0x18115F1C)
+ lw t7, 0(t6)
+ nop
+ li t8, 0x80000080
+ and t9, t7, t8
+
+default_pmu:
+ li t5, 0x80 /* default 0x031c4386 */
+ bne t8, t9, otp_end
+
+fetch_otp:
+ srl t8, t7, 0x18
+ li t1, 0xf
+ and t2, t1, t7 /* USB */
+ and t5, t1, t8 /* PMU */
+
+check_pmu:
+ li t0, 0x4 /* PMU range should be 0x4~0xa */
+ bgt t0, t5, default_pmu
+ nop
+ li t0, 0xa /* PMU range should be 0x4~0xa */
+ blt t0, t5, default_pmu
+ nop
+ li t0, 0x4
+ sll t5, t5, t0
+
+otp_end:
+#endif
+
+#if 1 /* Program PMU */
+#define PMU_TEST_NO 1000
+ li t6, KSEG1ADDR(0x18116C40)
+ li t9, 0xbd000010
+ li t0, 0
+ li t1, 0
+ li t2, 0
+ li t3, PMU_TEST_NO
+ sw t3, 12(t9)
+
+pmu_loop0:
+ beq zero, t3, pmu_loop0_end
+ nop
+ addi t3, t3, -1
+ li t7, 0x10180000 /* ldo_tune 0x3 */
+ nop
+ sw t7, 4(t6)
+ nop
+ lw t8, 4(t6)
+ nop
+ beq t8, t7, pmu_loop0_end
+ nop
+ addiu t0, t0, 1
+ b pmu_loop0
+ nop
+
+pmu_loop0_end:
+ li t3, PMU_TEST_NO
+
+pmu_loop1:
+ beq zero, t3, pmu_loop1_end
+ nop
+ addi t3, t3, -1
+ //li t7, 0x031c4326 /* 1.100V */
+ //li t7, 0x031c4336 /* 1.125V */
+ //li t7, 0x031c4346 /* 1.150V */
+ //li t7, 0x031c4356 /* 1.175V */
+ //li t7, 0x031c4366 /* 1.200V */
+ //li t7, 0x031c4376 /* 1.225V */
+ li t7, 0x031c4386 /* 1.250V (DEFAULT) */
+ //li t7, 0x031c4396 /* 1.275V */
+ //li t7, 0x031c43a6 /* 1.300V */
+ nop
+
+#if 1 /* from OTP */
+ li t8, 0xFFFFFF0F
+ and t7, t7, t8
+ or t7, t7, t5
+#endif
+ sw t7, 0(t6)
+ nop
+ lw t8, 0(t6)
+ nop
+ beq t8, t7, pmu_loop1_end
+ nop
+ addiu t1, t1, 1
+ b pmu_loop1
+ nop
+
+pmu_loop1_end:
+ li t3, PMU_TEST_NO
+
+pmu_loop2:
+ beq zero, t3, pmu_loop2_end
+ nop
+ addi t3, t3, -1
+ li t7, 0x10380000 /* ldo_tune 0x3 */
+ nop
+ sw t7, 4(t6)
+ nop
+ lw t8, 4(t6)
+ nop
+ beq t8, t7, pmu_loop2_end
+ nop
+ addiu t2, t2, 1
+ b pmu_loop2
+ nop
+
+pmu_loop2_end:
+ sw t0, 0(t9)
+ nop
+ sw t1, 4(t9)
+ nop
+ sw t2, 8(t9)
+ nop
+#endif
+
+#if 1 /* Program ki, kd */
+// TODO: ??
+/* Program ki/kd */
+#if CONFIG_40MHZ_XTAL_SUPPORT
+ set_reg(0x18116244, 0x19e82f01)
+#else
+ set_reg(0x18116244, 0x18e82f01)
+#endif
+ nop
+
+/* Program phase shift */
+ li t6, KSEG1ADDR(0x18116248)
+ lw t7, 0(t6)
+ li t8, 0xc07fffff
+ and t7, t7, t8
+ li t8, 0x800000
+ or t7, t7, t8
+ sw t7, 0(t6)
+ nop
+#endif
+
+/* max AHB Master wait time out ... */
+ set_reg(0x1800009C, 0xfffff)
+ nop
+
+/*
+ * O/C recovery mode
+ *
+ * If RESET BUTTON is pressed and hold during power on
+ * we will use default PLL and clocks configuration (400/400/200)
+ *
+ * Using t0 and t1 (t1 indicates if recovery mode was turned on)
+ */
+pll_clock_control_oc_recovery:
+ li t0, KSEG1ADDR(AR7240_GPIO_IN)
+ lw t1, 0(t0)
+ and t1, t1, (1 << GPIO_RST_BUTTON_BIT)
+ recovery_jump(pll_clock_control_default)
+ nop
+
+#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
+/*
+ * PLL and CLOCK configuration from FLASH
+ *
+ * Using t0, t2 and t3 (t2 stores magic value from flash)
+ */
+pll_clock_control_flash:
+ li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
+ lw t2, 0(t0) // load PLL_IN_FLASH_MAGIC value from FLASH
+ bne t2, PLL_IN_FLASH_MAGIC, pll_clock_control // jump if we don't have PLL_MAGIC value in FLASH
+ nop
+ lw t3, 8(t0) // load CLOCK_CONTROL register value from FLASH
+ or t3, t3, 0x18004 // set BYPASS bit and make AHB_POST_DIV = 4
+ li t0, KSEG1ADDR(AR7240_CPU_CLOCK_CONTROL) // load CLOCK_CONTROL register address
+ sw t3, 0(t0) // store value in CLOCK_CONTROL register
+ j pll_settle_time // jump to pll_settle_time
+ nop
+#endif
+
+pll_clock_control:
+/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */
+/* in some cases, the SoC doesn't start with higher clock on AHB */
+ set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(SET_PLL_BYPASS(CPU_CLK_CONTROL_VAL)))
+ j pll_settle_time
+ nop
+
+pll_clock_control_default:
+/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */
+/* in some cases, the SoC doesn't start with higher clock on AHB */
+ set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(SET_PLL_BYPASS(CPU_CLK_CONTROL_VAL_DEFAULT)))
+ nop
+
+pll_settle_time:
+/* set SETTLE_TIME in CPU PLL */
+ set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL)
+ nop
+
+pll_unlock_handler_oc_recovery:
+ recovery_jump(pll_unlock_handler_default)
+ nop
+
+#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
+pll_unlock_handler_flash:
+ bne t2, PLL_IN_FLASH_MAGIC, pll_unlock_handler // jump if we don't have PLL_MAGIC value in FLASH
+ nop
+ li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
+ lw t3, 4(t0) // load CPU_PLL_CONFIG register value from FLASH
+ or t3, t3, 0x40000000 // set CPU_PLLPWD bit (power down for CPU PLL)
+ li t0, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) // load CPU_PLL_CONFIG register address
+ sw t3, 0(t0) // store value in CPU_PLL_CONFIG register
+ j wait_loop2 // jump to wait_loop2
+ nop
+#endif
+
+pll_unlock_handler:
+/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
+ set_reg(AR7240_CPU_PLL_CONFIG, SET_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL))
+ j wait_loop2
+ nop
+
+pll_unlock_handler_default:
+/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
+ set_reg(AR7240_CPU_PLL_CONFIG, SET_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL_DEFAULT))
+ nop
+
+wait_loop2:
+ li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
+ lw t7, 0(t6)
+ li t8, 0x80000000
+ and t7, t7, t8
+ bne zero, t7, wait_loop2
+ nop
+
+/* put frac bit19:10 configuration */
+/* TODO: do we need this? */
+ set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL)
+ nop
+
+pll_lock_handler_oc_recovery:
+ recovery_jump(pll_lock_handler_default)
+ nop
+
+#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
+pll_lock_handler_flash:
+ bne t2, PLL_IN_FLASH_MAGIC, pll_lock_handler // jump if we don't have PLL_MAGIC value in FLASH
+ nop
+ li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
+ lw t3, 4(t0) // load CPU_PLL_CONFIG register value from FLASH
+ li t0, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) // load CPU_PLL_CONFIG register address
+ sw t3, 0(t0) // store value in CPU_PLL_CONFIG register
+ j wait_loop3 // jump to wait_loop3
+ nop
+#endif
+
+pll_lock_handler:
+/* clear PLL power down bit in CPU PLL configuration */
+ set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL)
+ j wait_loop3
+ nop
+
+pll_lock_handler_default:
+/* clear PLL power down bit in CPU PLL configuration */
+ set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL_DEFAULT)
+ nop
+
+wait_loop3:
+/* wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
+ li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
+ lw t7, 0(t6)
+ li t8, 0x80000000
+ and t7, t7, t8
+ bne zero, t7, wait_loop3
+ nop
+
+/* confirm DDR PLL lock */
+ li t3, 100
+ li t4, 0
+
+start_meas0:
+ addi t4, t4, 1
+ bgt t4, t3, pll_unlock_handler_oc_recovery
+ nop
+ li t5, 5
+
+start_meas:
+ li t6, KSEG1ADDR(0x18116248)
+ lw t7, 0(t6)
+ li t8, 0xBFFFFFFF
+ and t7, t7, t8
+ sw t7, 0(t6)
+ nop
+
+/* delay */
+ li t9, 10
+
+delayloop0:
+ subu t9, t9, 1
+ bne t9, zero, delayloop0
+ nop
+ li t8, 0x40000000
+ or t7, t7, t8
+ sw t7, 0(t6)
+ nop
+
+meas_done_statue:
+ li t6, KSEG1ADDR(0x1811624C)
+ lw t7, 0(t6)
+ li t8, 0x8
+ and t7, t7, t8
+ beq zero, t7, meas_done_statue
+ nop
+
+meas_result:
+ li t6, KSEG1ADDR(0x18116248)
+ lw t7, 0(t6)
+ li t8, 0x007FFFF8
+ and t7, t7, t8
+ srl t7, t7, 3
+ li t8, 0x4000
+ bgt t7, t8, start_meas0
+ nop
+ addi t5, t5, -1
+ bne zero, t5, start_meas
+ nop
+
+pll_clear_bypass_oc_recovery:
+ recovery_jump(pll_clear_bypass_default)
+ nop
+
+#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
+pll_clear_bypass_flash:
+ bne t2, PLL_IN_FLASH_MAGIC, pll_clear_bypass // jump if we don't have PLL_MAGIC value in FLASH
+ nop
+ li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
+ lw t3, 8(t0) // load CLOCK_CONTROL register value from FLASH
+ li t0, KSEG1ADDR(AR7240_CPU_CLOCK_CONTROL) // load CLOCK_CONTROL register address
+ sw t3, 0(t0) // store value in CLOCK_CONTROL register
+ j end // jump to end
+ nop
+#endif
+
+pll_clear_bypass:
+/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
+ set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL)
+ j end
+ nop
+
+pll_clear_bypass_default:
+/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
+ set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL_DEFAULT)
+ nop
+
+/* Sync mode, Set Bit 8 of DDR Tap Conrtol 3 register */
+/*
+ * TODO: something is wrong here?
+ * There is no AR7240_DDR_TAP_CONTROL3 in AR9331 datasheet!
+ */
+/*
+ set_reg(AR7240_DDR_TAP_CONTROL3, 0x10105);
+ nop
+*/
+
+end:
+ jr ra
+ nop
+++ /dev/null
-/*
- * Startup Code for MIPS32 CPU-core
- *
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
- .globl hornet_ddr_init
- .text
- .align 4
-
-#define set_mem(_mem, _val) \
- li t9, _mem; \
- sw _val, 0(t9);
-
-//============================================
-// init DDR1 parameter before rel_start
-//===========================================
-hornet_ddr_init:
- // 0x18000000 (DDR_CONFIG, p. 54)
- // CFG_DDR_CONFIG_VAL = 0x7fbc8cd0 (ap121.h)
- li t8, CFG_DDR_CONFIG_VAL;
- set_mem(0xB8000000, t8);
-
- // 0x18000004 (DDR_CONFIG2, p. 55)
- // CFG_DDR_CONFIG2_VAL = 0x99d0e6a8 (ap121.h)
- li t8, CFG_DDR_CONFIG2_VAL;
- set_mem(0xB8000004, t8);
-
-/*
- * WR720N v3 (CH version) has wrong bootstrap configuration,
- * so the memory type cannot be recognized automatically
- */
-#if !defined(CONFIG_FOR_TPLINK_WR720N_V3)
-mem_type:
- // TODO: what about SDRAM?
- // 0x180600AC (BOOT_STRAP, p. 81)
- li t8, 0xB80600AC // load BOOT_STRAP reg address
- lw t9, 0(t8) // and its value
- li t8, 0x2000 // 0x2000 -> BIT13 is set
- and t9, t9, t8
- beq t9, zero, ddr1_config // jump if we have DDR1
-
-ddr2_config:
- // Enable DDR2
- // 0x1800008C (DDR_DDR2_CONFIG, p. 58)
- li t8, 0xA59;
- set_mem(0xB800008C, t8);
-
- // Precharge All
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x8;
- set_mem(0xB8000010, t8);
-
- // Disable High Temperature Self-Refresh Rate
- // 0x18000090 (DDR_EMR2, p. 58)
- li t8, 0x0;
- set_mem(0xB8000090, t8);
-
- // Extended Mode Register 2 Set (EMR2S)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x10;
- set_mem(0xB8000010, t8);
-
- // 0x18000094 (DDR_EMR3, p. 58)
- li t8, 0x0;
- set_mem(0xB8000094, t8);
-
- // Extended Mode Register 3 Set (EMR3S)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x20;
- set_mem(0xB8000010, t8);
-
- // Enable DLL
- // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
- li t8, 0x0;
- set_mem(0xB800000C, t8);
-
- // Extended Mode Register Set (EMRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x2;
- set_mem(0xB8000010, t8);
-
- // Reset DLL
- // 0x18000008 (DDR_MODE_REGISTER, p. 55)
- li t8, 0x100;
- set_mem(0xB8000008, t8);
-
- // Mode Register Set (MRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x1;
- set_mem(0xB8000010, t8);
-
- // Precharge All
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x8;
- set_mem(0xB8000010, t8);
-
- // Auto Refresh
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x4;
- set_mem(0xB8000010, t8);
-
- // Auto Refresh
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x4;
- set_mem(0xB8000010, t8);
-
- // Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8
- // 0x18000008 (DDR_MODE_REGISTER, p. 55)
- li t8, 0xa33;
- set_mem(0xB8000008, t8);
-
- // Mode Register Set (MRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x1;
- set_mem(0xB8000010, t8);
-
- // E7,E8,E9 equal to 1(Enable OCD defaults), Enable DLL, Reduced Drive Strength
- // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
- li t8, 0x382;
- set_mem(0xB800000C, t8);
-
- // Extended Mode Register Set (EMRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x2;
- set_mem(0xB8000010, t8);
-
- // E7,E8,E9 equal to 0(OCD exit), Enable DLL, Reduced Drive Strength
- // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
- li t8, 0x402;
- set_mem(0xB800000C, t8);
-
- // Extended Mode Register Set (EMRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x2;
- set_mem(0xB8000010, t8);
-
- // Refresh control. Bit 14 is enable. Bits<13:0> Refresh time
- // 0x18000014 (DDR_REFRESH, p. 56)
- li t8, CFG_DDR_REFRESH_VAL;
- set_mem(0xB8000014, t8);
-
- // DQS 0 Tap Control (needs tuning)
- // 0x1800001C (TAP_CONTROL_0, p. 56)
- li t8, CFG_DDR_TAP0_VAL;
- set_mem(0xB800001C, t8);
-
- // DQS 1 Tap Control (needs tuning)
- // 0x18000020 (TAP_CONTROL_1, p. 57)
- li t8, CFG_DDR_TAP1_VAL;
- set_mem(0xB8000020, t8);
-
- // For 16-bit DDR
- // 0x18000018 (DDR_RD_DATA_THIS_CYCLE, p. 56)
- li t8, 0x00ff;
- set_mem(0xB8000018, t8);
-
- nop
- jr ra
-#endif /* !defined(CONFIG_FOR_TPLINK_WR720N_V3) */
-
-ddr1_config:
- // Precharge All
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x8;
- set_mem(0xB8000010, t8);
-
- // 0x18000008 (DDR_MODE_REGISTER, p. 55)
- li t8, CFG_DDR_MODE_VAL_INIT;
- set_mem(0xB8000008, t8);
-
- // Write Mode Word in DDR
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x1;
- set_mem(0xB8000010, t8);
-
- // Enable DLL, High drive strength from DDR
- // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
- li t8, 0x2;
- set_mem(0xB800000C, t8);
-
- // Write Extended Mode Word of DDR
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x2;
- set_mem(0xB8000010, t8);
-
- // Precharge All
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x8;
- set_mem(0xB8000010, t8);
-
- // DLL out of reset, CAS Latency 3
- // 0x18000008 (DDR_MODE_REGISTER, p. 55)
- li t8, CFG_DDR_MODE_VAL;
- set_mem(0xB8000008, t8);
-
- // Write mode word
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x1;
- set_mem(0xB8000010, t8);
-
- // Refresh control. Bit 14 is enable. Bits<13:0> Refresh time
- // 0x18000014 (DDR_REFRESH, p. 56)
- li t8, CFG_DDR_REFRESH_VAL;
- set_mem(0xB8000014, t8);
-
- // DQS 0 Tap Control (needs tuning)
- // 0x1800001C (TAP_CONTROL_0, p. 56)
- li t8, CFG_DDR_TAP0_VAL;
- set_mem(0xB800001C, t8);
-
- // DQS 1 Tap Control (needs tuning)
- // 0x18000020 (TAP_CONTROL_1, p. 57)
- li t8, CFG_DDR_TAP1_VAL;
- set_mem(0xB8000020, t8);
-
- // For 16-bit DDR
- // 0x18000018 (DDR_RD_DATA_THIS_CYCLE, p. 56)
- li t8, 0x00ff;
- set_mem(0xB8000018, t8);
-
- nop
- jr ra
-
-/*
- * void hornet_ddr_tap_init(void)
- *
- * This "function" is used to find the tap settings for the DDR
- */
- .globl hornet_ddr_tap_init
- .ent hornet_ddr_tap_init
-hornet_ddr_tap_init: /* { */
-
- li t1,0x80500000
- li t0,0xffffffff
-
- sw t0,0x0(t1)
- sw t0,0x4(t1)
- sw t0,0x8(t1)
- sw t0,0xc(t1)
-
- nop
- nop
-
-ddr_pat_init:
- li t8, 0xa0002000
- li t0, 0x00
- li t1, 0x100
-
-write_loop_start:
- andi t2, t0, 0x03
-
-pat_000:
- li t3, 0x00
- bne t2, t3,pat_001
- li t9, 0x00000000
- sw t9, 0x0 (t8)
- b pat_004
-
-pat_001:
- li t3, 0x01
- bne t2, t3,pat_002
- li t9, 0x0000ffff
- sw t9, 0x0 (t8)
- b pat_004
-
-pat_002:
- li t3, 0x02
- bne t2, t3,pat_003
- li t9, 0xffff0000
- sw t9, 0x0 (t8)
- b pat_004
-
-pat_003:
- li t3, 0x03
- bne t2, t3,pat_004
- li t9, 0xffffffff
- sw t9, 0x0 (t8)
-
-pat_004:
- andi t2, t0, 0x0c
- li t3, 0x00
- bne t2, t3,pat_005
- li t9, 0x00000000
- sw t9, 0x4 (t8)
- b pat_008
-
-pat_005:
- li t3, 0x04
- bne t2, t3,pat_006
- li t9, 0x0000ffff
- sw t9, 0x4 (t8)
- b pat_008
-
-pat_006:
- li t3, 0x08
- bne t2, t3,pat_007
- li t9, 0xffff0000
- sw t9, 0x4 (t8)
- b pat_008
-
-pat_007:
- li t3, 0x0c
- bne t2, t3,pat_008
- li t9, 0xffffffff
- sw t9, 0x4 (t8)
-
-pat_008:
- andi t2, t0, 0x30
- li t3, 0x00
- bne t2, t3,pat_009
- li t9, 0x00000000
- sw t9, 0x8 (t8)
- b pat_00c
-
-pat_009:
- li t3, 0x10
- bne t2, t3,pat_00a
- li t9, 0x0000ffff
- sw t9, 0x8 (t8)
- b pat_00c
-
-pat_00a:
- li t3, 0x20
- bne t2, t3,pat_00b
- li t9, 0xffff0000
- sw t9, 0x8 (t8)
- b pat_00c
-
-pat_00b:
- li t3, 0x30
- bne t2, t3,pat_00c
- li t9, 0xffffffff
- sw t9, 0x8 (t8)
-
-pat_00c:
- andi t2, t0, 0xc0
- li t3, 0x00
- bne t2, t3,pat_00d
- li t9, 0x00000000
- sw t9, 0xc (t8)
- b pat_done
-
-pat_00d:
- li t3, 0x40
- bne t2, t3,pat_00e
- li t9, 0x0000ffff
- sw t9, 0xc (t8)
- b pat_done
-
-pat_00e:
- li t3, 0x80
- bne t2, t3,pat_00f
- li t9, 0xffff0000
- sw t9, 0xc (t8)
- b pat_done
-
-pat_00f:
- li t3, 0xc0
- bne t2, t3,pat_done
- li t9, 0xffffffff
- sw t9, 0xc (t8)
-
-pat_done:
- addiu t0, t0, 0x1
- addiu t8, t8, 0x10
- bne t0, t1, write_loop_start
-
-###### ddr init over #########
-
- li a0, 0xa0002000
- li a1, 0x80002000 ### Start address of the pattern 200
- li a2, 0x80003000 ### End Address of the pattern 220
- li t0, 0xb800001c ## Tap settings addr
- lw a3, 0x0(t0) ## loading default tap value
- nop
- ori t0, a3, 0x0
- nop
- li t1, 0x1 ## $t1=1 indicates increasing tap value, 0 = decreasing
-
-load_tap:
- li t7, 0x2
- #li t7, 0x200 ## No. of times read has to happen for 1 tap setting
- li t8, 0xb8000000 #### Loading Tap Setting
- sw t0, 0x1c(t8)
- nop
- sw t0, 0x20(t8)
- nop
- #if 0 /* Hornet doesn't have DQS2, DQS3*/
- sw t0, 0x24(t8)
- nop
- sw t0, 0x28(t8)
- nop
- #endif
-
-###### t0 stores current tap setting under test
-###### t1 indicates increment or decrement of tap
-
-pat_read:
- ori t2, a0, 0x0
- nop
- ori t3, a1, 0x0
- nop
- ori t4, a2, 0x0
- nop
-
-tap_addr_loop:
- lw t5, 0x0(t2)
- nop
- lw t6, 0x0(t3)
- nop
- nop
-
- bne t5, t6, tap_fail # jump to fail if not equal
- nop
- nop
- nop
-
- addiu t2, t2, 0x4 #incrementing addr
- addiu t3, t3, 0x4
- nop
- nop
-
- bne t3, t4, tap_addr_loop # compare new addr if end addr not reached
- nop
-
- addiu t7, t7, -1 # read passed for all locations once hence decrement t7
- nop
- bnez t7, pat_read # t7 = 0 represents passing of all locations for given tap
- nop
- nop
-
- bnez t1, tap_incr # increment tap if t1 = 1
- nop
- nop
-
- bnez t0, tap_decr ## $t0=0 implies tap=0 works
- nop ## so low limit=0, else decrement tap value
- nop
- li t8, 0x80500000 ## assigning lower limit = 0
- sw t0, 0x0(t8)
- add t9, t9, t0 ##adding lower limit to upper limit (used to calc mid value)
- nop
- nop
-
- b tap_calc
- nop
- nop
-
-tap_decr: # decrement t0 by 1 and move to loading this new tap
- addiu t0, t0 , -1
- nop
- b load_tap
- nop
- nop
-
-tap_incr:
- addiu t0, t0 , 0x1
- nop
- xori v1, t0, 0x20 # limiting upper limit to 0x20
- nop
- bnez v1, load_tap
- nop
- nop
- b up_limit
- nop
- nop
-
-tap_fail:
- bnez t1, up_limit # t1=0 means lower limit detected @ fail else upper limit
- nop
- nop
- nop
- addiu t0, t0, 0x1
- nop
- li t8, 0x80500000 # storing lower limit
- nop
- sw t0, 0x0(t8)
- add t9, t9, t0 # storing lower limit# adding lower limit and upper limit
- nop
- nop
- nop
-
- b tap_calc
- nop
- nop
-
-up_limit:
- addiu t0, t0, -1
- li t1, 0x0 ## changing to decreasing tap mode
- li t8, 0x80500000 ## storing upper limit
- sw t0, 0x4(t8)
- ori t9, t0, 0x0
- nop
- nop
- nop
-
- ori t0, a3, 0x0 # loading default tap value
- nop
- b load_tap
- nop
- nop
-
-tap_calc: ## calculating mid value of the tap, storing DQS0, DQS1 in 0x80500008, 0x8050000c resp.
- li t7, 0x2
- nop
- div t9, t7
- nop
- mfhi t6
- mflo t5
- nop
- nop
- add t6, t6, t5
- li t8, 0x80500000
- nop
- sw t5, 0x8(t8)
- nop
- sw t6, 0xc(t8)
- nop
- nop
- li t8, 0xb8000000 #### Loading Tap Setting
- nop
- sw t5, 0x1c(t8)
- nop
- sw t6, 0x20(t8)
- nop
- nop
- nop
-
-end:
- nop
- nop
- nop
- jr ra
-
- .end hornet_ddr_tap_init
-/* } */
projects / oweals / u-boot_mod.git / commitdiff