// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*/
#include <common.h>
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
+ const char *conn;
+
+ /* Do NOT apply fixup for backplane modes specified in DT */
+ if (phyc == PHY_INTERFACE_MODE_XGMII) {
+ conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(conn))
+ return 0;
+ }
return fdt_setprop_string(blob, offset, "phy-connection-type",
phy_string_for_interface(phyc));
}
#define DCFG_PORSR1 0x000
#define DCFG_PORSR1_RCW_SRC 0xff800000
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
+#define DCFG_RCWSR12 0x12c
+#define DCFG_RCWSR12_SDHC_SHIFT 24
+#define DCFG_RCWSR12_SDHC_MASK 0x7
#define DCFG_RCWSR13 0x130
+#define DCFG_RCWSR13_SDHC_SHIFT 3
+#define DCFG_RCWSR13_SDHC_MASK 0x7
#define DCFG_RCWSR13_DSPI (0 << 8)
#define DCFG_RCWSR15 0x138
#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
+ const char *conn;
+
+ /* Do NOT apply fixup for backplane modes specified in DT */
+ if (phyc == PHY_INTERFACE_MODE_XGMII) {
+ conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(conn))
+ return 0;
+ }
return fdt_setprop_string(blob, offset, "phy-connection-type",
phy_string_for_interface(phyc));
}
print_ddr_info(0);
}
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+ void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
+ char esdhc1_path[] = "/soc/mmc@2140000";
+ char esdhc2_path[] = "/soc/mmc@2150000";
+ char dspi1_path[] = "/soc/spi@2100000";
+ char dspi2_path[] = "/soc/spi@2110000";
+ u32 mux_sdhc1, mux_sdhc2;
+ u32 io = 0;
+
+ /*
+ * The PMUX IO-expander for mux select is used to control
+ * the muxing of various onboard interfaces.
+ */
+
+ io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
+ mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
+
+ /* Disable esdhc1/dspi1 if not selected. */
+ if (mux_sdhc1 != 0)
+ do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ if (mux_sdhc1 != 2)
+ do_fixup_by_path(blob, dspi1_path, "status", "disabled",
+ sizeof("disabled"), 1);
+
+ io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
+ mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
+
+ /* Disable esdhc2/dspi2 if not selected. */
+ if (mux_sdhc2 != 0)
+ do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ if (mux_sdhc2 != 2)
+ do_fixup_by_path(blob, dspi2_path, "status", "disabled",
+ sizeof("disabled"), 1);
+
+ return 0;
+}
+
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*/
#include <common.h>
enum fm_port port, int offset)
{
struct fixed_link f_link;
- const u32 *handle;
- const char *prop = NULL;
- int off;
+ const char *phyconn;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
switch (port) {
"qsgmii");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
(port == FM1_10GEC1 || port == FM1_10GEC2)) {
- handle = fdt_getprop(fdt, offset, "phy-handle", NULL);
- prop = NULL;
- if (handle) {
- off = fdt_node_offset_by_phandle(fdt,
- fdt32_to_cpu(*handle));
- prop = fdt_getprop(fdt, off, "backplane-mode", NULL);
- }
- if (!prop || strcmp(prop, "10gbase-kr")) {
+ phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(phyconn)) {
+ /* Backplane KR mode: skip fixups */
+ printf("Interface %d in backplane KR mode\n", port);
+ } else {
/* XFI interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
*/
return offset;
}
+ phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(phy_string)) {
+ /* Backplane KR mode: skip fixups */
+ printf("Interface %d in backplane KR mode\n", dpmac_id);
+ return 0;
+ }
+
ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
if (ret)
printf("%d@%s %d\n", __LINE__, __func__, ret);
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
- u64 gic_lpi_base;
+ u64 __maybe_unused gic_lpi_base;
ft_cpu_setup(blob, bd);
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
*/
char buf[32] = "serdes-1,";
struct fixed_link f_link;
int media_type = 0;
+ const char *phyconn;
int off;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
}
if (!media_type) {
- /* fixed-link is used for XFI fiber cable */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link,
- sizeof(f_link));
+ phyconn = fdt_getprop(fdt, offset,
+ "phy-connection-type",
+ NULL);
+ if (is_backplane_mode(phyconn)) {
+ /* Backplane KR mode: skip fixups */
+ printf("Interface %d in backplane KR mode\n",
+ port);
+ } else {
+ /* fixed-link for XFI fiber cable */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link",
+ &f_link, sizeof(f_link));
+ }
} else {
/* set property for copper cable */
off = fdt_node_offset_by_compat_reg(fdt,
It is also strongly encouraged to also enable CONFIG_MTD to get full
partition support.
+config CMD_UBI_RENAME
+ bool "Enable rename"
+ depends on CMD_UBI
+ default n
+ help
+ Enable a "ubi" command to rename ubi volume:
+ ubi rename <oldname> <newname>
+
config CMD_UBIFS
tristate "Enable UBIFS - Unsorted block images filesystem commands"
depends on CMD_UBI
#endif
#if defined(CONFIG_DM_I2C)
-int eeprom_i2c_bus;
+static int eeprom_i2c_bus;
#endif
__weak int eeprom_write_enable(unsigned dev_addr, int state)
return err;
}
+static int ubi_rename_vol(char *oldname, char *newname)
+{
+ struct ubi_volume *vol;
+ struct ubi_rename_entry rename;
+ struct ubi_volume_desc desc;
+ struct list_head list;
+
+ vol = ubi_find_volume(oldname);
+ if (!vol) {
+ printf("%s: volume %s doesn't exist\n", __func__, oldname);
+ return ENODEV;
+ }
+
+ printf("Rename UBI volume %s to %s\n", oldname, newname);
+
+ if (ubi->ro_mode) {
+ printf("%s: ubi device is in read-only mode\n", __func__);
+ return EROFS;
+ }
+
+ rename.new_name_len = strlen(newname);
+ strcpy(rename.new_name, newname);
+ rename.remove = 0;
+ desc.vol = vol;
+ desc.mode = 0;
+ rename.desc = &desc;
+ INIT_LIST_HEAD(&rename.list);
+ INIT_LIST_HEAD(&list);
+ list_add(&rename.list, &list);
+
+ return ubi_rename_volumes(ubi, &list);
+}
+
static int ubi_volume_continue_write(char *volume, void *buf, size_t size)
{
int err = 1;
return ubi_remove_vol(argv[2]);
}
+ if (IS_ENABLED(CONFIG_CMD_UBI_RENAME) && !strncmp(argv[1], "rename", 6))
+ return ubi_rename_vol(argv[2], argv[3]);
+
if (strncmp(argv[1], "skipcheck", 9) == 0) {
/* E.g., change skip_check flag */
if (argc == 4) {
" - Read volume to address with size\n"
"ubi remove[vol] volume"
" - Remove volume\n"
+#if IS_ENABLED(CONFIG_CMD_UBI_RENAME)
+ "ubi rename oldname newname\n"
+#endif
"ubi skipcheck volume on/off - Set or clear skip_check flag in volume header\n"
"[Legends]\n"
" volume: character name\n"
i2c-gpio driver unless your system can cope with this limitation.
Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
+config SYS_I2C_IPROC
+ bool "Broadcom I2C driver"
+ depends on DM_I2C
+ help
+ Broadcom I2C driver.
+ Add support for Broadcom I2C driver.
+ Say yes here to to enable the Broadco I2C driver.
+
config SYS_I2C_FSL
bool "Freescale I2C bus driver"
depends on DM_I2C
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
+obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Broadcom
+ *
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include "errno.h"
+#include <i2c.h>
+#include "iproc_i2c.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct iproc_i2c_regs {
+ u32 cfg_reg;
+ u32 timg_cfg;
+ u32 addr_reg;
+ u32 mstr_fifo_ctrl;
+ u32 slv_fifo_ctrl;
+ u32 bitbng_ctrl;
+ u32 blnks[6]; /* Not to be used */
+ u32 mstr_cmd;
+ u32 slv_cmd;
+ u32 evt_en;
+ u32 evt_sts;
+ u32 mstr_datawr;
+ u32 mstr_datard;
+ u32 slv_datawr;
+ u32 slv_datard;
+};
+
+struct iproc_i2c {
+ struct iproc_i2c_regs __iomem *base; /* register base */
+ int bus_speed;
+ int i2c_init_done;
+};
+
+/* Function to read a value from specified register. */
+static unsigned int iproc_i2c_reg_read(u32 *reg_addr)
+{
+ unsigned int val;
+
+ val = readl((void *)(reg_addr));
+ return cpu_to_le32(val);
+}
+
+/* Function to write a value ('val') in to a specified register. */
+static int iproc_i2c_reg_write(u32 *reg_addr, unsigned int val)
+{
+ val = cpu_to_le32(val);
+ writel(val, (void *)(reg_addr));
+ return 0;
+}
+
+#if defined(DEBUG)
+static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
+{
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ unsigned int regval;
+
+ debug("\n----------------------------------------------\n");
+ debug("%s: Dumping SMBus registers...\n", __func__);
+
+ regval = iproc_i2c_reg_read(&base->cfg_reg);
+ debug("CCB_SMB_CFG_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->timg_cfg);
+ debug("CCB_SMB_TIMGCFG_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->addr_reg);
+ debug("CCB_SMB_ADDR_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->mstr_fifo_ctrl);
+ debug("CCB_SMB_MSTRFIFOCTL_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->slv_fifo_ctrl);
+ debug("CCB_SMB_SLVFIFOCTL_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->bitbng_ctrl);
+ debug("CCB_SMB_BITBANGCTL_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+ debug("CCB_SMB_MSTRCMD_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->slv_cmd);
+ debug("CCB_SMB_SLVCMD_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->evt_en);
+ debug("CCB_SMB_EVTEN_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->evt_sts);
+ debug("CCB_SMB_EVTSTS_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->mstr_datawr);
+ debug("CCB_SMB_MSTRDATAWR_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->mstr_datard);
+ debug("CCB_SMB_MSTRDATARD_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->slv_datawr);
+ debug("CCB_SMB_SLVDATAWR_REG=0x%08X\n", regval);
+
+ regval = iproc_i2c_reg_read(&base->slv_datard);
+ debug("CCB_SMB_SLVDATARD_REG=0x%08X\n", regval);
+
+ debug("----------------------------------------------\n\n");
+ return 0;
+}
+#else
+static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
+{
+ return 0;
+}
+#endif
+
+/*
+ * Function to ensure that the previous transaction was completed before
+ * initiating a new transaction. It can also be used in polling mode to
+ * check status of completion of a command
+ */
+static int iproc_i2c_startbusy_wait(struct iproc_i2c *bus_prvdata)
+{
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ unsigned int regval;
+
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+
+ /* Check if an operation is in progress. During probe it won't be.
+ * But when shutdown/remove was called we want to make sure that
+ * the transaction in progress completed
+ */
+ if (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
+ unsigned int i = 0;
+
+ do {
+ mdelay(10);
+ i++;
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+
+ /* If start-busy bit cleared, exit the loop */
+ } while ((regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) &&
+ (i < IPROC_SMB_MAX_RETRIES));
+
+ if (i >= IPROC_SMB_MAX_RETRIES) {
+ pr_err("%s: START_BUSY bit didn't clear, exiting\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ }
+ return 0;
+}
+
+/*
+ * This function set clock frequency for SMBus block. As per hardware
+ * engineering, the clock frequency can be changed dynamically.
+ */
+static int iproc_i2c_set_clk_freq(struct iproc_i2c *bus_prvdata)
+{
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ unsigned int regval;
+
+ regval = iproc_i2c_reg_read(&base->timg_cfg);
+
+ switch (bus_prvdata->bus_speed) {
+ case I2C_SPEED_STANDARD_RATE:
+ regval &= ~CCB_SMB_TIMGCFG_MODE400_MASK;
+ break;
+
+ case I2C_SPEED_FAST_RATE:
+ regval |= CCB_SMB_TIMGCFG_MODE400_MASK;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ iproc_i2c_reg_write(&base->timg_cfg, regval);
+ return 0;
+}
+
+static int iproc_i2c_init(struct udevice *bus)
+{
+ struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ unsigned int regval;
+
+ debug("\nEntering %s\n", __func__);
+
+ /* Put controller in reset */
+ regval = iproc_i2c_reg_read(&base->cfg_reg);
+ regval |= CCB_SMB_CFG_RST_MASK;
+ regval &= ~CCB_SMB_CFG_SMBEN_MASK;
+ iproc_i2c_reg_write(&base->cfg_reg, regval);
+
+ /* Wait 100 usec as per spec */
+ udelay(100);
+
+ /* bring controller out of reset */
+ regval &= ~CCB_SMB_CFG_RST_MASK;
+ iproc_i2c_reg_write(&base->cfg_reg, regval);
+
+ /* Flush Tx, Rx FIFOs. Note we are setting the Rx FIFO threshold to 0.
+ * May be OK since we are setting RX_EVENT and RX_FIFO_FULL interrupts
+ */
+ regval = CCB_SMB_MSTRRXFIFOFLSH_MASK | CCB_SMB_MSTRTXFIFOFLSH_MASK;
+ iproc_i2c_reg_write(&base->mstr_fifo_ctrl, regval);
+
+ /* Enable SMbus block. Note, we are setting MASTER_RETRY_COUNT to zero
+ * since there will be only one master
+ */
+ regval = iproc_i2c_reg_read(&base->cfg_reg);
+ regval |= CCB_SMB_CFG_SMBEN_MASK;
+ iproc_i2c_reg_write(&base->cfg_reg, regval);
+
+ /* Set default clock frequency */
+ iproc_i2c_set_clk_freq(bus_prvdata);
+
+ /* Disable intrs */
+ iproc_i2c_reg_write(&base->evt_en, 0);
+
+ /* Clear intrs (W1TC) */
+ regval = iproc_i2c_reg_read(&base->evt_sts);
+ iproc_i2c_reg_write(&base->evt_sts, regval);
+
+ bus_prvdata->i2c_init_done = 1;
+
+ iproc_dump_i2c_regs(bus_prvdata);
+ debug("%s: Init successful\n", __func__);
+
+ return 0;
+}
+
+/*
+ * This function copies data to SMBus's Tx FIFO. Valid for write transactions
+ * only
+ *
+ * base_addr: Mapped address of this SMBus instance
+ * dev_addr: SMBus (I2C) device address. We are assuming 7-bit addresses
+ * initially
+ * info: Data to copy in to Tx FIFO. For read commands, the size should be
+ * set to zero by the caller
+ *
+ */
+static void iproc_i2c_write_trans_data(struct iproc_i2c *bus_prvdata,
+ unsigned short dev_addr,
+ struct iproc_xact_info *info)
+{
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ unsigned int regval;
+ unsigned int i;
+ unsigned int num_data_bytes = 0;
+
+ debug("%s: dev_addr=0x%X cmd_valid=%d cmd=0x%02x size=%u proto=%d buf[] %x\n",
+ __func__, dev_addr, info->cmd_valid,
+ info->command, info->size, info->smb_proto, info->data[0]);
+
+ /* Write SMBus device address first */
+ /* Note, we are assuming 7-bit addresses for now. For 10-bit addresses,
+ * we may have one more write to send the upper 3 bits of 10-bit addr
+ */
+ iproc_i2c_reg_write(&base->mstr_datawr, dev_addr);
+
+ /* If the protocol needs command code, copy it */
+ if (info->cmd_valid)
+ iproc_i2c_reg_write(&base->mstr_datawr, info->command);
+
+ /* Depending on the SMBus protocol, we need to write additional
+ * transaction data in to Tx FIFO. Refer to section 5.5 of SMBus
+ * spec for sequence for a transaction
+ */
+ switch (info->smb_proto) {
+ case SMBUS_PROT_RECV_BYTE:
+ /* No additional data to be written */
+ num_data_bytes = 0;
+ break;
+
+ case SMBUS_PROT_SEND_BYTE:
+ num_data_bytes = info->size;
+ break;
+
+ case SMBUS_PROT_RD_BYTE:
+ case SMBUS_PROT_RD_WORD:
+ case SMBUS_PROT_BLK_RD:
+ /* Write slave address with R/W~ set (bit #0) */
+ iproc_i2c_reg_write(&base->mstr_datawr,
+ dev_addr | 0x1);
+ num_data_bytes = 0;
+ break;
+
+ case SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL:
+ iproc_i2c_reg_write(&base->mstr_datawr,
+ dev_addr | 0x1 |
+ CCB_SMB_MSTRWRSTS_MASK);
+ num_data_bytes = 0;
+ break;
+
+ case SMBUS_PROT_WR_BYTE:
+ case SMBUS_PROT_WR_WORD:
+ /* No additional bytes to be written.
+ * Data portion is written in the
+ * 'for' loop below
+ */
+ num_data_bytes = info->size;
+ break;
+
+ case SMBUS_PROT_BLK_WR:
+ /* 3rd byte is byte count */
+ iproc_i2c_reg_write(&base->mstr_datawr, info->size);
+ num_data_bytes = info->size;
+ break;
+
+ default:
+ return;
+ }
+
+ /* Copy actual data from caller, next. In general, for reads,
+ * no data is copied
+ */
+ for (i = 0; num_data_bytes; --num_data_bytes, i++) {
+ /* For the last byte, set MASTER_WR_STATUS bit */
+ regval = (num_data_bytes == 1) ?
+ info->data[i] | CCB_SMB_MSTRWRSTS_MASK :
+ info->data[i];
+
+ iproc_i2c_reg_write(&base->mstr_datawr, regval);
+ }
+}
+
+static int iproc_i2c_data_send(struct iproc_i2c *bus_prvdata,
+ unsigned short addr,
+ struct iproc_xact_info *info)
+{
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ int rc, retry = 3;
+ unsigned int regval;
+
+ /* Make sure the previous transaction completed */
+ rc = iproc_i2c_startbusy_wait(bus_prvdata);
+
+ if (rc < 0) {
+ pr_err("%s: Send: bus is busy, exiting\n", __func__);
+ return rc;
+ }
+
+ /* Write transaction bytes to Tx FIFO */
+ iproc_i2c_write_trans_data(bus_prvdata, addr, info);
+
+ /* Program master command register (0x30) with protocol type and set
+ * start_busy_command bit to initiate the write transaction
+ */
+ regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
+ CCB_SMB_MSTRSTARTBUSYCMD_MASK;
+
+ iproc_i2c_reg_write(&base->mstr_cmd, regval);
+
+ /* Check for Master status */
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+ while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
+ mdelay(10);
+ if (retry-- <= 0)
+ break;
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+ }
+
+ /* If start_busy bit cleared, check if there are any errors */
+ if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
+ /* start_busy bit cleared, check master_status field now */
+ regval &= CCB_SMB_MSTRSTS_MASK;
+ regval >>= CCB_SMB_MSTRSTS_SHIFT;
+
+ if (regval != MSTR_STS_XACT_SUCCESS) {
+ /* Error We can flush Tx FIFO here */
+ pr_err("%s: ERROR: Error in transaction %u, exiting\n",
+ __func__, regval);
+ return -EREMOTEIO;
+ }
+ }
+
+ return 0;
+}
+
+static int iproc_i2c_data_recv(struct iproc_i2c *bus_prvdata,
+ unsigned short addr,
+ struct iproc_xact_info *info,
+ unsigned int *num_bytes_read)
+{
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ int rc, retry = 3;
+ unsigned int regval;
+
+ /* Make sure the previous transaction completed */
+ rc = iproc_i2c_startbusy_wait(bus_prvdata);
+
+ if (rc < 0) {
+ pr_err("%s: Receive: Bus is busy, exiting\n", __func__);
+ return rc;
+ }
+
+ /* Program all transaction bytes into master Tx FIFO */
+ iproc_i2c_write_trans_data(bus_prvdata, addr, info);
+
+ /* Program master command register (0x30) with protocol type and set
+ * start_busy_command bit to initiate the write transaction
+ */
+ regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
+ CCB_SMB_MSTRSTARTBUSYCMD_MASK | info->size;
+
+ iproc_i2c_reg_write(&base->mstr_cmd, regval);
+
+ /* Check for Master status */
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+ while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
+ udelay(1000);
+ if (retry-- <= 0)
+ break;
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+ }
+
+ /* If start_busy bit cleared, check if there are any errors */
+ if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
+ /* start_busy bit cleared, check master_status field now */
+ regval &= CCB_SMB_MSTRSTS_MASK;
+ regval >>= CCB_SMB_MSTRSTS_SHIFT;
+
+ if (regval != MSTR_STS_XACT_SUCCESS) {
+ /* We can flush Tx FIFO here */
+ pr_err("%s: Error in transaction %d, exiting\n",
+ __func__, regval);
+ return -EREMOTEIO;
+ }
+ }
+
+ /* Read received byte(s), after TX out address etc */
+ regval = iproc_i2c_reg_read(&base->mstr_datard);
+
+ /* For block read, protocol (hw) returns byte count,
+ * as the first byte
+ */
+ if (info->smb_proto == SMBUS_PROT_BLK_RD) {
+ int i;
+
+ *num_bytes_read = regval & CCB_SMB_MSTRRDDATA_MASK;
+
+ /* Limit to reading a max of 32 bytes only; just a safeguard.
+ * If # bytes read is a number > 32, check transaction set up,
+ * and contact hw engg. Assumption: PEC is disabled
+ */
+ for (i = 0;
+ (i < *num_bytes_read) && (i < I2C_SMBUS_BLOCK_MAX);
+ i++) {
+ /* Read Rx FIFO for data bytes */
+ regval = iproc_i2c_reg_read(&base->mstr_datard);
+ info->data[i] = regval & CCB_SMB_MSTRRDDATA_MASK;
+ }
+ } else {
+ /* 1 Byte data */
+ *info->data = regval & CCB_SMB_MSTRRDDATA_MASK;
+ *num_bytes_read = 1;
+ }
+
+ return 0;
+}
+
+static int i2c_write_byte(struct iproc_i2c *bus_prvdata,
+ u8 devaddr, u8 regoffset, u8 value)
+{
+ int rc;
+ struct iproc_xact_info info;
+
+ devaddr <<= 1;
+
+ info.cmd_valid = 1;
+ info.command = (unsigned char)regoffset;
+ info.data = &value;
+ info.size = 1;
+ info.flags = 0;
+ info.smb_proto = SMBUS_PROT_WR_BYTE;
+ /* Refer to i2c_smbus_write_byte params passed. */
+ rc = iproc_i2c_data_send(bus_prvdata, devaddr, &info);
+
+ if (rc < 0) {
+ pr_err("%s: %s error accessing device 0x%X\n",
+ __func__, "Write", devaddr);
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+int i2c_write(struct udevice *bus,
+ uchar chip, uint regaddr, int alen, uchar *buffer, int len)
+{
+ struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
+ int i, data_len;
+ u8 *data;
+
+ if (len > 256) {
+ pr_err("I2C write: address out of range\n");
+ return 1;
+ }
+
+ if (len < 1) {
+ pr_err("I2C write: Need offset addr and value\n");
+ return 1;
+ }
+
+ /* buffer contains offset addr followed by value to be written */
+ regaddr = buffer[0];
+ data = &buffer[1];
+ data_len = len - 1;
+
+ for (i = 0; i < data_len; i++) {
+ if (i2c_write_byte(bus_prvdata, chip, regaddr + i, data[i])) {
+ pr_err("I2C write (%d): I/O error\n", i);
+ iproc_i2c_init(bus);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static int i2c_read_byte(struct iproc_i2c *bus_prvdata,
+ u8 devaddr, u8 regoffset, u8 *value)
+{
+ int rc;
+ struct iproc_xact_info info;
+ unsigned int num_bytes_read = 0;
+
+ devaddr <<= 1;
+
+ info.cmd_valid = 1;
+ info.command = (unsigned char)regoffset;
+ info.data = value;
+ info.size = 1;
+ info.flags = 0;
+ info.smb_proto = SMBUS_PROT_RD_BYTE;
+ /* Refer to i2c_smbus_read_byte for params passed. */
+ rc = iproc_i2c_data_recv(bus_prvdata, devaddr, &info, &num_bytes_read);
+
+ if (rc < 0) {
+ pr_err("%s: %s error accessing device 0x%X\n",
+ __func__, "Read", devaddr);
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+int i2c_read(struct udevice *bus,
+ uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
+ int i;
+
+ if (len > 256) {
+ pr_err("I2C read: address out of range\n");
+ return 1;
+ }
+
+ for (i = 0; i < len; i++) {
+ if (i2c_read_byte(bus_prvdata, chip, addr + i, &buffer[i])) {
+ pr_err("I2C read: I/O error\n");
+ iproc_i2c_init(bus);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static int iproc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ int ret = 0;
+
+ debug("%s: %d messages\n", __func__, nmsgs);
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ if (msg->flags & I2C_M_RD)
+ ret = i2c_read(bus, msg->addr, 0, 0,
+ msg->buf, msg->len);
+ else
+ ret = i2c_write(bus, msg->addr, 0, 0,
+ msg->buf, msg->len);
+ }
+
+ return ret;
+}
+
+static int iproc_i2c_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ u32 regval;
+
+ debug("\n%s: Entering chip probe\n", __func__);
+
+ /* Init internal regs, disable intrs (and then clear intrs), set fifo
+ * thresholds, etc.
+ */
+ if (!bus_prvdata->i2c_init_done)
+ iproc_i2c_init(bus);
+
+ regval = (chip_addr << 1);
+ iproc_i2c_reg_write(&base->mstr_datawr, regval);
+ regval = ((SMBUS_PROT_QUICK_CMD << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
+ (1 << CCB_SMB_MSTRSTARTBUSYCMD_SHIFT));
+ iproc_i2c_reg_write(&base->mstr_cmd, regval);
+
+ do {
+ udelay(100);
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+ regval &= CCB_SMB_MSTRSTARTBUSYCMD_MASK;
+ } while (regval);
+
+ regval = iproc_i2c_reg_read(&base->mstr_cmd);
+
+ if ((regval & CCB_SMB_MSTRSTS_MASK) != 0)
+ return -1;
+
+ iproc_dump_i2c_regs(bus_prvdata);
+ debug("%s: chip probe successful\n", __func__);
+
+ return 0;
+}
+
+static int iproc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
+
+ bus_prvdata->bus_speed = speed;
+ return iproc_i2c_set_clk_freq(bus_prvdata);
+}
+
+/**
+ * i2c_get_bus_speed - get i2c bus speed
+ *
+ * This function returns the speed of operation in Hz
+ */
+int iproc_i2c_get_bus_speed(struct udevice *bus)
+{
+ struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
+ struct iproc_i2c_regs *base = bus_prvdata->base;
+ unsigned int regval;
+ int ret = 0;
+
+ regval = iproc_i2c_reg_read(&base->timg_cfg);
+ regval = (regval & CCB_SMB_TIMGCFG_MODE400_MASK) >>
+ CCB_SMB_TIMGCFG_MODE400_SHIFT;
+
+ switch (regval) {
+ case 0:
+ ret = I2C_SPEED_STANDARD_RATE;
+ break;
+ case 1:
+ ret = I2C_SPEED_FAST_RATE;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int iproc_i2c_probe(struct udevice *bus)
+{
+ return iproc_i2c_init(bus);
+}
+
+static int iproc_i2c_ofdata_to_platdata(struct udevice *bus)
+{
+ struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
+ int node = dev_of_offset(bus);
+ const void *blob = gd->fdt_blob;
+
+ bus_prvdata->base = map_physmem(devfdt_get_addr(bus),
+ sizeof(void *),
+ MAP_NOCACHE);
+
+ bus_prvdata->bus_speed =
+ fdtdec_get_int(blob, node, "bus-frequency",
+ I2C_SPEED_STANDARD_RATE);
+
+ return 0;
+}
+
+static const struct dm_i2c_ops iproc_i2c_ops = {
+ .xfer = iproc_i2c_xfer,
+ .probe_chip = iproc_i2c_probe_chip,
+ .set_bus_speed = iproc_i2c_set_bus_speed,
+ .get_bus_speed = iproc_i2c_get_bus_speed,
+};
+
+static const struct udevice_id iproc_i2c_ids[] = {
+ { .compatible = "brcm,iproc-i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(iproc_i2c) = {
+ .name = "iproc_i2c",
+ .id = UCLASS_I2C,
+ .of_match = iproc_i2c_ids,
+ .ofdata_to_platdata = iproc_i2c_ofdata_to_platdata,
+ .probe = iproc_i2c_probe,
+ .priv_auto_alloc_size = sizeof(struct iproc_i2c),
+ .ops = &iproc_i2c_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Broadcom
+ *
+ */
+
+#ifndef __IPROC_I2C_H__
+#define __IPROC_I2C_H__
+
+/* Registers */
+#define CCB_SMB_CFG_REG 0x0
+
+#define CCB_SMB_CFG_RST_MASK 0x80000000
+#define CCB_SMB_CFG_RST_SHIFT 31
+
+#define CCB_SMB_CFG_SMBEN_MASK 0x40000000
+#define CCB_SMB_CFG_SMBEN_SHIFT 30
+
+#define CCB_SMB_CFG_BITBANGEN_MASK 0x20000000
+#define CCB_SMB_CFG_BITBANGEN_SHIFT 29
+
+#define CCB_SMB_CFG_EN_NIC_SMBADDR0_MASK 0x10000000
+#define CCB_SMB_CFG_EN_NIC_SMBADDR0_SHIFT 28
+
+#define CCB_SMB_CFG_PROMISCMODE_MASK 0x08000000
+#define CCB_SMB_CFG_PROMISCMODE_SHIFT 27
+
+#define CCB_SMB_CFG_TSTMPCNTEN_MASK 0x04000000
+#define CCB_SMB_CFG_TSTMPCNTEN_SHIFT 26
+
+#define CCB_SMB_CFG_MSTRRTRYCNT_MASK 0x000F0000
+#define CCB_SMB_CFG_MSTRRTRYCNT_SHIFT 16
+
+#define CCB_SMB_TIMGCFG_REG 0x4
+
+#define CCB_SMB_TIMGCFG_MODE400_MASK 0x80000000
+#define CCB_SMB_TIMGCFG_MODE400_SHIFT 31
+
+#define CCB_SMB_TIMGCFG_RNDSLVSTR_MASK 0x7F000000
+#define CCB_SMB_TIMGCFG_RNDSLVSTR_SHIFT 24
+
+#define CCB_SMB_TIMGCFG_PERSLVSTR_MASK 0x00FF0000
+#define CCB_SMB_TIMGCFG_PERSLVSTR_SHIFT 16
+
+#define CCB_SMB_TIMGCFG_IDLTIME_MASK 0x0000FF00
+#define CCB_SMB_TIMGCFG_IDLTIME_SHIFT 8
+
+#define CCB_SMB_ADDR_REG 0x8
+
+#define CCB_SMB_EN_NIC_SMBADDR3_MASK 0x80000000
+#define CCB_SMB_EN_NIC_SMBADDR3_SHIFT 31
+
+#define CCB_SMB_NIC_SMBADDR3_MASK 0x7F000000
+#define CCB_SMB_NIC_SMBADDR3_SHIFT 24
+
+#define CCB_SMB_EN_NIC_SMBADDR2_MASK 0x00800000
+#define CCB_SMB_EN_NIC_SMBADDR2_SHIFT 23
+
+#define CCB_SMB_NIC_SMBADDR2_MASK 0x007F0000
+#define CCB_SMB_NIC_SMBADDR2_SHIFT 16
+
+#define CCB_SMB_EN_NIC_SMBADDR1_MASK 0x00008000
+#define CCB_SMB_EN_NIC_SMBADDR1_SHIFT 15
+
+#define CCB_SMB_NIC_SMBADDR1_MASK 0x00007F00
+#define CCB_SMB_NIC_SMBADDR1_SHIFT 8
+
+#define CCB_SMB_EN_NIC_SMBADDR0_MASK 0x00000080
+#define CCB_SMB_EN_NIC_SMBADDR0_SHIFT 7
+
+#define CCB_SMB_NIC_SMBADDR0_MASK 0x0000007F
+#define CCB_SMB_NIC_SMBADDR0_SHIFT 0
+
+#define CCB_SMB_MSTRFIFOCTL_REG 0xC
+
+#define CCB_SMB_MSTRRXFIFOFLSH_MASK 0x80000000
+#define CCB_SMB_MSTRRXFIFOFLSH_SHIFT 31
+
+#define CCB_SMB_MSTRTXFIFOFLSH_MASK 0x40000000
+#define CCB_SMB_MSTRTXFIFOFLSH_SHIFT 30
+
+#define CCB_SMB_MSTRRXPKTCNT_MASK 0x007F0000
+#define CCB_SMB_MSTRRXPKTCNT_SHIFT 16
+
+#define CCB_SMB_MSTRRXFIFOTHR_MASK 0x00003F00
+#define CCB_SMB_MSTRRXFIFOTHR_SHIFT 8
+
+#define CCB_SMB_SLVFIFOCTL_REG 0x10
+
+#define CCB_SMB_SLVRXFIFOFLSH_MASK 0x80000000
+#define CCB_SMB_SLVRXFIFOFLSH_SHIFT 31
+
+#define CCB_SMB_SLVTXFIFOFLSH_MASK 0x40000000
+#define CCB_SMB_SLVTXFIFOFLSH_SHIFT 30
+
+#define CCB_SMB_SLVRXPKTCNT_MASK 0x007F0000
+#define CCB_SMB_SLVRXPKTCNT_SHIFT 16
+
+#define CCB_SMB_SLVRXFIFOTHR_MASK 0x00003F00
+#define CCB_SMB_SLVRXFIFOTHR_SHIFT 8
+
+#define CCB_SMB_BITBANGCTL_REG 0x14
+
+#define CCB_SMB_SMBCLKIN_MASK 0x80000000
+#define CCB_SMB_SMBCLKIN_SHIFT 31
+
+#define CCB_SMB_SMBCLKOUTEN_MASK 0x40000000
+#define CCB_SMB_SMBCLKOUTEN_SHIFT 30
+
+#define CCB_SMB_SMBDATAIN_MASK 0x20000000
+#define CCB_SMB_SMBDATAIN_SHIFT 29
+
+#define CCB_SMB_SMBDATAOUTEN_MASK 0x10000000
+#define CCB_SMB_SMBDATAOUTEN_SHIFT 28
+
+#define CCB_SMB_MSTRCMD_REG 0x30
+
+#define CCB_SMB_MSTRSTARTBUSYCMD_MASK 0x80000000
+#define CCB_SMB_MSTRSTARTBUSYCMD_SHIFT 31
+
+#define CCB_SMB_MSTRABORT_MASK 0x40000000
+#define CCB_SMB_MSTRABORT_SHIFT 30
+
+#define CCB_SMB_MSTRSTS_MASK 0x0E000000
+#define CCB_SMB_MSTRSTS_SHIFT 25
+
+#define CCB_SMB_MSTRSMBUSPROTO_MASK 0x00001E00
+#define CCB_SMB_MSTRSMBUSPROTO_SHIFT 9
+
+#define CCB_SMB_MSTRPEC_MASK 0x00000100
+#define CCB_SMB_MSTRPEC_SHIFT 8
+
+#define CCB_SMB_MSTRRDBYTECNT_MASK 0x000000FF
+#define CCB_SMB_MSTRRDBYTECNT_SHIFT 0
+
+#define CCB_SMB_SLVCMD_REG 0x34
+
+#define CCB_SMB_SLVSTARTBUSYCMD_MASK 0x80000000
+#define CCB_SMB_SLVSTARTBUSYCMD_SHIFT 31
+
+#define CCB_SMB_SLVABORT_MASK 0x40000000
+#define CCB_SMB_SLVABORT_SHIFT 30
+
+#define CCB_SMB_SLVSTS_MASK 0x03800000
+#define CCB_SMB_SLVSTS_SHIFT 23
+
+#define CCB_SMB_SLVPEC_MASK 0x00000100
+#define CCB_SMB_SLVPEC_SHIFT 8
+
+#define CCB_SMB_EVTEN_REG 0x38
+
+#define CCB_SMB_MSTRRXFIFOFULLEN_MASK 0x80000000
+#define CCB_SMB_MSTRRXFIFOFULLEN_SHIFT 31
+
+#define CCB_SMB_MSTRRXFIFOTHRHITEN_MASK 0x40000000
+#define CCB_SMB_MSTRRXFIFOTHRHITEN_SHIFT 30
+
+#define CCB_SMB_MSTRRXEVTEN_MASK 0x20000000
+#define CCB_SMB_MSTRRXEVTEN_SHIFT 29
+
+#define CCB_SMB_MSTRSTARTBUSYEN_MASK 0x10000000
+#define CCB_SMB_MSTRSTARTBUSYEN_SHIFT 28
+
+#define CCB_SMB_MSTRTXUNDEN_MASK 0x08000000
+#define CCB_SMB_MSTRTXUNDEN_SHIFT 27
+
+#define CCB_SMB_SLVRXFIFOFULLEN_MASK 0x04000000
+#define CCB_SMB_SLVRXFIFOFULLEN_SHIFT 26
+
+#define CCB_SMB_SLVRXFIFOTHRHITEN_MASK 0x02000000
+#define CCB_SMB_SLVRXFIFOTHRHITEN_SHIFT 25
+
+#define CCB_SMB_SLVRXEVTEN_MASK 0x01000000
+#define CCB_SMB_SLVRXEVTEN_SHIFT 24
+
+#define CCB_SMB_SLVSTARTBUSYEN_MASK 0x00800000
+#define CCB_SMB_SLVSTARTBUSYEN_SHIFT 23
+
+#define CCB_SMB_SLVTXUNDEN_MASK 0x00400000
+#define CCB_SMB_SLVTXUNDEN_SHIFT 22
+
+#define CCB_SMB_SLVRDEVTEN_MASK 0x00200000
+#define CCB_SMB_SLVRDEVTEN_SHIFT 21
+
+#define CCB_SMB_EVTSTS_REG 0x3C
+
+#define CCB_SMB_MSTRRXFIFOFULLSTS_MASK 0x80000000
+#define CCB_SMB_MSTRRXFIFOFULLSTS_SHIFT 31
+
+#define CCB_SMB_MSTRRXFIFOTHRHITSTS_MASK 0x40000000
+#define CCB_SMB_MSTRRXFIFOTHRHITSTS_SHIFT 30
+
+#define CCB_SMB_MSTRRXEVTSTS_MASK 0x20000000
+#define CCB_SMB_MSTRRXEVTSTS_SHIFT 29
+
+#define CCB_SMB_MSTRSTARTBUSYSTS_MASK 0x10000000
+#define CCB_SMB_MSTRSTARTBUSYSTS_SHIFT 28
+
+#define CCB_SMB_MSTRTXUNDSTS_MASK 0x08000000
+#define CCB_SMB_MSTRTXUNDSTS_SHIFT 27
+
+#define CCB_SMB_SLVRXFIFOFULLSTS_MASK 0x04000000
+#define CCB_SMB_SLVRXFIFOFULLSTS_SHIFT 26
+
+#define CCB_SMB_SLVRXFIFOTHRHITSTS_MASK 0x02000000
+#define CCB_SMB_SLVRXFIFOTHRHITSTS_SHIFT 25
+
+#define CCB_SMB_SLVRXEVTSTS_MASK 0x01000000
+#define CCB_SMB_SLVRXEVTSTS_SHIFT 24
+
+#define CCB_SMB_SLVSTARTBUSYSTS_MASK 0x00800000
+#define CCB_SMB_SLVSTARTBUSYSTS_SHIFT 23
+
+#define CCB_SMB_SLVTXUNDSTS_MASK 0x00400000
+#define CCB_SMB_SLVTXUNDSTS_SHIFT 22
+
+#define CCB_SMB_SLVRDEVTSTS_MASK 0x00200000
+#define CCB_SMB_SLVRDEVTSTS_SHIFT 21
+
+#define CCB_SMB_MSTRDATAWR_REG 0x40
+
+#define CCB_SMB_MSTRWRSTS_MASK 0x80000000
+#define CCB_SMB_MSTRWRSTS_SHIFT 31
+
+#define CCB_SMB_MSTRWRDATA_MASK 0x000000FF
+#define CCB_SMB_MSTRWRDATA_SHIFT 0
+
+#define CCB_SMB_MSTRDATARD_REG 0x44
+
+#define CCB_SMB_MSTRRDSTS_MASK 0xC0000000
+#define CCB_SMB_MSTRRDSTS_SHIFT 30
+
+#define CCB_SMB_MSTRRDPECERR_MASK 0x20000000
+#define CCB_SMB_MSTRRDPECERR_SHIFT 29
+
+#define CCB_SMB_MSTRRDDATA_MASK 0x000000FF
+#define CCB_SMB_MSTRRDDATA_SHIFT 0
+
+#define CCB_SMB_SLVDATAWR_REG 0x48
+
+#define CCB_SMB_SLVWRSTS_MASK 0x80000000
+#define CCB_SMB_SLVWRSTS_SHIFT 31
+
+#define CCB_SMB_SLVWRDATA_MASK 0x000000FF
+#define CCB_SMB_SLVWRDATA_SHIFT 0
+
+#define CCB_SMB_SLVDATARD_REG 0x4C
+
+#define CCB_SMB_SLVRDSTS_MASK 0xC0000000
+#define CCB_SMB_SLVRDSTS_SHIFT 30
+
+#define CCB_SMB_SLVRDERRSTS_MASK 0x30000000
+#define CCB_SMB_SLVRDERRSTS_SHIFT 28
+
+#define CCB_SMB_SLVRDDATA_MASK 0x000000FF
+#define CCB_SMB_SLVRDDATA_SHIFT 0
+
+/* --Registers-- */
+
+/* Transaction error codes defined in Master command register (0x30) */
+#define MSTR_STS_XACT_SUCCESS 0
+#define MSTR_STS_LOST_ARB 1
+#define MSTR_STS_NACK_FIRST_BYTE 2
+
+/* NACK on a byte other than
+ * the first byte
+ */
+#define MSTR_STS_NACK_NON_FIRST_BYTE 3
+
+#define MSTR_STS_TTIMEOUT_EXCEEDED 4
+#define MSTR_STS_TX_TLOW_MEXT_EXCEEDED 5
+#define MSTR_STS_RX_TLOW_MEXT_EXCEEDED 6
+
+/* SMBUS protocol values defined in register 0x30 */
+#define SMBUS_PROT_QUICK_CMD 0
+#define SMBUS_PROT_SEND_BYTE 1
+#define SMBUS_PROT_RECV_BYTE 2
+#define SMBUS_PROT_WR_BYTE 3
+#define SMBUS_PROT_RD_BYTE 4
+#define SMBUS_PROT_WR_WORD 5
+#define SMBUS_PROT_RD_WORD 6
+#define SMBUS_PROT_BLK_WR 7
+#define SMBUS_PROT_BLK_RD 8
+#define SMBUS_PROT_PROC_CALL 9
+#define SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL 10
+
+/* SMBUS Block speed mode */
+#define SMBUS_BLOCK_MODE_100 0
+#define SMBUS_BLOCK_MODE_400 1
+
+#define BUS_BUSY_COUNT 100000 /* Number can be changed later */
+#define IPROC_I2C_INVALID_ADDR 0xFF
+#define IPROC_SMB_MAX_RETRIES 35
+#define I2C_SMBUS_BLOCK_MAX 32
+#define GETREGFLDVAL(regval, mask, startbit) \
+ (((regval) & (mask)) >> (startbit))
+
+/* This enum will be used to notify the user of status of a data transfer
+ * request
+ */
+enum iproc_smb_error_code {
+ I2C_NO_ERR = 0,
+ I2C_TIMEOUT_ERR = 1,
+
+ /* Invalid parameter(s) passed to the driver */
+ I2C_INVALID_PARAM_ERR = 2,
+
+ /* The driver API was called before the present
+ * transfer was completed
+ */
+ I2C_OPER_IN_PROGRESS = 3,
+
+ /* Transfer aborted unexpectedly, for example a NACK
+ * received, before last byte was read/written
+ */
+ I2C_OPER_ABORT_ERR = 4,
+
+ /* Feature or function not supported
+ * (e.g., 10-bit addresses, or clock speeds
+ * other than 100KHz, 400KHz)
+ */
+ I2C_FUNC_NOT_SUPPORTED = 5,
+};
+
+/* Structure used to pass information to read/write functions. */
+struct iproc_xact_info {
+ unsigned char command;
+ unsigned char *data;
+ unsigned int size;
+ unsigned short flags; /* used for specifying PEC, 10-bit addresses */
+ unsigned char smb_proto; /* SMBus protocol */
+ unsigned int cmd_valid; /* true if command is valid else false */
+};
+
+#endif /* __IPROC_I2C_H__ */
devices. It is x width I2C multiplexer which enables to partitioning
I2C bus and connect multiple devices with the same address to the same
I2C controller where driver handles proper routing to target i2c
- device. Supported chips are PCA9543, PCA9544, PCA9547, PCA9548 and
- PCA9646.
+ device. Supported chips are PCA9543, PCA9544, PCA9546, PCA9547,
+ PCA9548 and PCA9646.
config I2C_MUX_GPIO
tristate "GPIO-based I2C multiplexer"
enum pca_type {
PCA9543,
PCA9544,
+ PCA9546,
PCA9547,
PCA9548,
PCA9646
.muxtype = pca954x_ismux,
.width = 4,
},
+ [PCA9546] = {
+ .muxtype = pca954x_isswi,
+ .width = 4,
+ },
[PCA9547] = {
.enable = 0x8,
.muxtype = pca954x_ismux,
static const struct udevice_id pca954x_ids[] = {
{ .compatible = "nxp,pca9543", .data = PCA9543 },
{ .compatible = "nxp,pca9544", .data = PCA9544 },
+ { .compatible = "nxp,pca9546", .data = PCA9546 },
{ .compatible = "nxp,pca9547", .data = PCA9547 },
{ .compatible = "nxp,pca9548", .data = PCA9548 },
{ .compatible = "nxp,pca9646", .data = PCA9646 },
if (src == BOOT_SOURCE_IFC_NOR) {
addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
CONFIG_SYS_FSL_IFC_BASE);
+#ifdef CONFIG_CMD_NAND
} else if (src == BOOT_SOURCE_IFC_NAND) {
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
CONFIG_SYS_FMAN_FW_ADDR, rc);
}
+#endif
} else if (src == BOOT_SOURCE_QSPI_NOR) {
struct spi_flash *ucode_flash;
"kernel_size=0x2800000\0" \
"kernelheader_size=0x40000\0" \
"console=ttyS0,115200\0" \
+ "BOARD=ls1012afrwy\0" \
BOOTENV \
"boot_scripts=ls1012afrwy_boot.scr\0" \
"boot_script_hdr=hdr_ls1012afrwy_bs.out\0" \
"source ${scriptaddr}\0" \
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
- "bootm $load_addr#$board\0" \
+ "bootm $load_addr#$BOARD\0" \
"qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
- "bootm $load_addr#$board\0" \
+ "bootm $load_addr#$BOARD\0" \
"sd_bootcmd=pfe stop; echo Trying load from sd card..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0"
+ "bootm $load_addr#$BOARD\0"
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
* Andy Fleming <afleming@gmail.com>
*
* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
[PHY_INTERFACE_MODE_NONE] = "",
};
+/* Backplane modes:
+ * are considered a sub-type of phy_interface_t: XGMII
+ * and are specified in "phy-connection-type" with one of the following strings
+ */
+static const char * const backplane_mode_strings[] = {
+ "10gbase-kr",
+ "40gbase-kr4",
+};
+
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
return phy_interface_strings[i];
}
+static inline bool is_backplane_mode(const char *phyconn)
+{
+ int i;
+
+ if (!phyconn)
+ return false;
+ for (i = 0; i < ARRAY_SIZE(backplane_mode_strings); i++) {
+ if (!strcmp(phyconn, backplane_mode_strings[i]))
+ return true;
+ }
+ return false;
+}
+
#endif /* _PHY_INTERFACE_H */
projects / oweals / u-boot.git / commitdiff