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raw | patch | inline | side by side (parent: d450805)
Fix AR933x PLL/clock profiles
authorPiotr Dymacz <pepe2k@gmail.com>
Mon, 21 Mar 2016 01:11:43 +0000 (02:11 +0100)
committerPiotr Dymacz <pepe2k@gmail.com>
Mon, 21 Mar 2016 01:11:43 +0000 (02:11 +0100)
u-boot/include/cmd_qcaclk.h patch | blob | history
u-boot/include/soc/ar933x_pll_init.h patch | blob | history

diff --git a/u-boot/include/cmd_qcaclk.h b/u-boot/include/cmd_qcaclk.h
index da9c92aee201af86e47b6ccb17dd3bf38d62f8a5..26dd05df723529c647a9f223863f9506c938a982 100755 (executable)
--- a/u-boot/include/cmd_qcaclk.h
+++ b/u-boot/include/cmd_qcaclk.h
@@ -70,60 +70,65 @@ typedef struct {
 static const clk_profile clk_profiles[] = {
        #if (SOC_TYPE & QCA_AR933X_SOC)
        {
+               /* Tested! */
                100, 100, 50, 12,
                _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
                {
-                       _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1),
-                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+                       _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1),
+                       _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
                        _ar933x_cpu_pll_dither_frac_reg_val(0)
                }, {
-                       _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1),
-                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+                       _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1),
+                       _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
                        _ar933x_cpu_pll_dither_frac_reg_val(0)
                },
        },
        {
-               100, 100, 100, 16,
-               _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+               /* Tested! */
+               100, 100, 100, 25,
+               _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
                {
-                       _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1),
-                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
+                       _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1),
+                       _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4),
                        _ar933x_cpu_pll_dither_frac_reg_val(0)
                }, {
-                       _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1),
-                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
+                       _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1),
+                       _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4),
                        _ar933x_cpu_pll_dither_frac_reg_val(0)
                },
        },
        {
-               150, 150, 150, 18,
-               _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+               /* Tested! */
+               150, 150, 150, 25,
+               _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
                {
-                       _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1),
-                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
+                       _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
+                       _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2),
                        _ar933x_cpu_pll_dither_frac_reg_val(0)
                }, {
-                       _ar933x_cpu_pll_cfg_reg_val(7, 1, 1, 1),
-                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
-                       _ar933x_cpu_pll_dither_frac_reg_val(512)
+                       _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1),
+                       _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2),
+                       _ar933x_cpu_pll_dither_frac_reg_val(0)
                },
        },
        {
-               160, 160, 80, 13,
-               _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+               /* Tested! */
+               160, 160, 80, 20,
+               _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
                {
-                       _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1),
-                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
-                       _ar933x_cpu_pll_dither_frac_reg_val(820)
+                       _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
+                       _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
+                       _ar933x_cpu_pll_dither_frac_reg_val(615)
                }, {
-                       _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1),
-                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+                       _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1),
+                       _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
                        _ar933x_cpu_pll_dither_frac_reg_val(0)
                },
        },
        {
-               200, 200, 100, 16,
-               _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+               /* Tested! */
+               200, 200, 100, 25,
+               _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
                {
                        _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2),
                        _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
@@ -135,6 +140,7 @@ static const clk_profile clk_profiles[] = {
                },
        },
        {
+               /* Tested! */
                200, 200, 200, 25,
                _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
                {
@@ -148,8 +154,9 @@ static const clk_profile clk_profiles[] = {
                },
        },
        {
-               300, 300, 150, 15,
-               _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
+               /* Tested! */
+               300, 300, 150, 25,
+               _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
                {
                        _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
                        _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
@@ -161,8 +168,9 @@ static const clk_profile clk_profiles[] = {
                },
        },
        {
-               350, 350, 175, 17,
-               _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
+               /* Tested! */
+               350, 350, 175, 29,
+               _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
                {
                        _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1),
                        _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
@@ -174,6 +182,7 @@ static const clk_profile clk_profiles[] = {
                },
        },
        {
+               /* Tested! */
                400, 400, 200, 25,
                _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
                {
@@ -187,6 +196,7 @@ static const clk_profile clk_profiles[] = {
                },
        },
        {
+               /* Tested! */
                500, 500, 250, 25,
                _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
                {
diff --git a/u-boot/include/soc/ar933x_pll_init.h b/u-boot/include/soc/ar933x_pll_init.h
index 867699990b687d7bccb45f83079f58969809fa0a..99082404838547edb3c6be771c175505734f816a 100644 (file)
--- a/u-boot/include/soc/ar933x_pll_init.h
+++ b/u-boot/include/soc/ar933x_pll_init.h
@@ -57,43 +57,44 @@
  */
 #if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50)
 
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
 
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
 
        #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
 
 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)
 
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
 
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
 
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
 
 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150)
 
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
 
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(7, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
-       #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
+
+       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 
 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)
 
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
-       #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+       #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
 
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
 
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
 
 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100)
 
@@ -103,7 +104,7 @@
        #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
        #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
 
 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200)
 
@@ -121,7 +122,7 @@
        #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
        #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 
 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175)
 
@@ -132,7 +133,7 @@
        #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
        #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 
 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200)
 
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