static const clk_profile clk_profiles[] = {
#if (SOC_TYPE & QCA_AR933X_SOC)
{
+ /* Tested! */
100, 100, 50, 12,
_ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
{
- _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1),
- _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
_ar933x_cpu_pll_dither_frac_reg_val(0)
}, {
- _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1),
- _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
_ar933x_cpu_pll_dither_frac_reg_val(0)
},
},
{
- 100, 100, 100, 16,
- _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ /* Tested! */
+ 100, 100, 100, 25,
+ _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
{
- _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1),
- _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
+ _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4),
_ar933x_cpu_pll_dither_frac_reg_val(0)
}, {
- _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1),
- _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
+ _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4),
_ar933x_cpu_pll_dither_frac_reg_val(0)
},
},
{
- 150, 150, 150, 18,
- _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ /* Tested! */
+ 150, 150, 150, 25,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
- _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1),
- _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
+ _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2),
_ar933x_cpu_pll_dither_frac_reg_val(0)
}, {
- _ar933x_cpu_pll_cfg_reg_val(7, 1, 1, 1),
- _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
- _ar933x_cpu_pll_dither_frac_reg_val(512)
+ _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
},
},
{
- 160, 160, 80, 13,
- _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ /* Tested! */
+ 160, 160, 80, 20,
+ _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
{
- _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1),
- _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
- _ar933x_cpu_pll_dither_frac_reg_val(820)
+ _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
}, {
- _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1),
- _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
_ar933x_cpu_pll_dither_frac_reg_val(0)
},
},
{
- 200, 200, 100, 16,
- _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ /* Tested! */
+ 200, 200, 100, 25,
+ _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
{
_ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2),
_ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
},
},
{
+ /* Tested! */
200, 200, 200, 25,
_ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
},
},
{
- 300, 300, 150, 15,
- _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
+ /* Tested! */
+ 300, 300, 150, 25,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
_ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
_ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
},
},
{
- 350, 350, 175, 17,
- _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
+ /* Tested! */
+ 350, 350, 175, 29,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
{
_ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1),
_ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
},
},
{
+ /* Tested! */
400, 400, 200, 25,
_ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
{
},
},
{
+ /* Tested! */
500, 500, 250, 25,
_ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
{
*/
#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1)
- #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1)
- #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1)
- #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1)
- #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
- #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1)
- #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(7, 1, 1, 1)
- #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
- #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1)
- #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
- #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
- #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1)
- #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
- #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
- #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
- #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
#define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
- #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200)