Move up DDR_RD_DATA_THIS_CYCLE register setup in new AR933x dram init code

diff --git a/u-boot/cpu/mips/ar7240/ar933x_dram.c b/u-boot/cpu/mips/ar7240/ar933x_dram.c
index 971a4fa420f9c1d87cdbf651bfdb36f9f80bbb5b..7d0ecbda2b39f8ad3101dda225c19672bfaf50d2 100644 (file)
--- a/u-boot/cpu/mips/ar7240/ar933x_dram.c
+++ b/u-boot/cpu/mips/ar7240/ar933x_dram.c
@@ -178,6 +178,9 @@ void qca_dram_init(void)
                                          _qca_ddr_cfg2_reg_val(0, 1, 0, 1, 6, 14, 8, 14, 7, 1));
 #endif
 
+       /* AR933x supports only 16-bit memory */
+       qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF);
+
        if (mem_type == RAM_MEMORY_TYPE_SDR) {
                /* Enable SDR */
                qca_soc_reg_write(QCA_SDR_CFG_REG, 1);
@@ -229,8 +232,5 @@ void qca_dram_init(void)
        /* Enable DDR refresh and setup refresh period */
        qca_dram_set_en_refresh();
 
-       /* AR933x supports only 16-bit memory */
-       qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF);
-
        ar933x_ddr_tap_tune();
 }