/*
* CPU_PLL_CONFIG and CPU_CLK_CONTROL registers values generator
*/
-#define MAKE_CPU_PLL_CONFIG_VAL(divint, refdiv, range, outdiv) (((0x3F & divint) << 10) | ((0x1F & refdiv) << 16) | ((0x1 & range) << 21) | ((0x7 & outdiv) << 23))
-#define MAKE_CPU_CLK_CONTROL_VAL(cpudiv, ddrdiv, ahbdiv) (((0x3 & (cpudiv - 1)) << 5) | ((0x3 & (ddrdiv - 1)) << 10) | ((0x3 & (ahbdiv - 1)) << 15))
+#define MAKE_AR9331_CPU_PLL_CONFIG_VAL(divint, refdiv, range, outdiv) ( ((0x3F & divint) << 10) | \
+ ((0x1F & refdiv) << 16) | \
+ ((0x1 & range) << 21) | \
+ ((0x7 & outdiv) << 23) )
+
+#define MAKE_AR9331_CPU_CLK_CONTROL_VAL(cpudiv, ddrdiv, ahbdiv) ( ((0x3 & (cpudiv - 1)) << 5) | \
+ ((0x3 & (ddrdiv - 1)) << 10) | \
+ ((0x3 & (ahbdiv - 1)) << 15) )
+
+#define MAKE_AR9331_SPI_CONTROL_VAL(spidiv) ( ((spidiv >> 1) - 1) | 0x40 )
/*
* Default values (400/400/200 MHz) for O/C recovery mode
*/
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
-#define CPU_CLK_CONTROL_VAL_DEFAULT MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+#define CPU_CLK_CONTROL_VAL_DEFAULT MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 20 (40 MHz * 20/2 = 400 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL_DEFAULT MAKE_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL_DEFAULT MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
#else
// DIV_INT = 32 (25 MHz * 32/2 = 400 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL_DEFAULT MAKE_CPU_PLL_CONFIG_VAL(32, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL_DEFAULT MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
-#define AR7240_SPI_CONTROL_DEFAULT 0x42
+#define AR7240_SPI_CONTROL_DEFAULT MAKE_AR9331_SPI_CONTROL_VAL(6)
#if (CFG_PLL_FREQ == CFG_PLL_200_200_100)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 20 (40 MHz * 20/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(20, 1, 0, 2)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2)
#else
// DIV_INT = 32 (25 MHz * 32/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(32, 1, 0, 2)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2)
#endif
// CLOCK_DIVIDER = 1 (SPI clock = 100 / 4 ~ 25 MHz)
- #define AR7240_SPI_CONTROL 0x41
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
#define CFG_HZ_FALLBACK (200000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_200_200_200)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 1)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 20 (40 MHz * 20/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(20, 1, 0, 2)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2)
#else
// DIV_INT = 32 (25 MHz * 32/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(32, 1, 0, 2)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (200000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_225_225_112)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 36 (25 MHz * 36/4 = 225 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(36, 1, 0, 2)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2)
#endif
// CLOCK_DIVIDER = 1 (SPI clock = 112 / 4 ~ 28 MHz)
- #define AR7240_SPI_CONTROL 0x41
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
#define CFG_HZ_FALLBACK (225000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_225_225_225)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 1)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 36 (25 MHz * 36/4 = 225 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(36, 1, 0, 2)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 225 / 8 ~ 28 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (225000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_250_250_125)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 25 (40 MHz * 25/4 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(25, 1, 0, 2)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2)
#else
// DIV_INT = 20 (25 MHz * 20/2 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 1 (SPI clock = 125 / 4 ~ 31 MHz)
- #define AR7240_SPI_CONTROL 0x41
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
#define CFG_HZ_FALLBACK (250000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_250_250_250)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 1)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 25 (40 MHz * 25/4 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(25, 1, 0, 2)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2)
#else
// DIV_INT = 20 (25 MHz * 20/2 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (250000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 15 (40 MHz * 15/2 = 300 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(15, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(15, 1, 0, 1)
#else
// DIV_INT = 24 (25 MHz * 24/2 = 300 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(24, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 150 / 6 ~ 25 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (300000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_325_325_162)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 26 (25 MHz * 26/2 = 325 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(26, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 162 / 6 ~ 27 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (325000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 28 (25 MHz * 28/2 = 350 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(28, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 175 / 6 ~ 29 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (350000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_360_360_180)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 18 (40 MHz * 18/2 = 360 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(18, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(18, 1, 0, 1)
#else
// DIV_INT = 29 (25 MHz * 28/2 = 362 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(29, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 180 / 6 ~ 30 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (360000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_380_380_190)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 19 (40 MHz * 19/2 = 380 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(19, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(19, 1, 0, 1)
#else
#define FREQUENCY_NOT_SUPPORTED
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 190 / 6 ~ 32 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (380000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_412_412_206)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 33 (25 MHz * 33/2 = 412 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(33, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(33, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 206 / 6 ~ 34 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (412000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_420_420_210)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 21 (40 MHz * 21/2 = 420 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(21, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(21, 1, 0, 1)
#else
#define FREQUENCY_NOT_SUPPORTED
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 210 / 6 ~ 35 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (420000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_425_425_212)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 34 (25 MHz * 34/2 = 425 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(34, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(34, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 212 / 6 ~ 35 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (425000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_437_437_218)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 35 (25 MHz * 35/2 = 437 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(35, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(35, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 218 / 8 ~ 27 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (437000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_440_440_220)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 22 (40 MHz * 22/2 = 440 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(22, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(22, 1, 0, 1)
#else
#define FREQUENCY_NOT_SUPPORTED
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 220 / 8 ~ 27 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (440000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_450_450_225)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 36 (25 MHz * 36/2 = 450 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(36, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 225 / 8 ~ 28 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (450000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_460_460_230)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 23 (40 MHz * 23/2 = 460 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(23, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(23, 1, 0, 1)
#else
// DIV_INT = 37 (25 MHz * 36/2 = 462 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(37, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(37, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 230 / 8 ~ 29 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (460000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_475_475_237)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 38 (25 MHz * 38/2 = 475 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(38, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(38, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 237 / 8 ~ 30 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (475000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_480_480_240)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 24 (40 MHz * 24/2 = 480 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(24, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1)
#else
#define FREQUENCY_NOT_SUPPORTED
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 240 / 8 ~ 30 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (480000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_487_487_243)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 39 (25 MHz * 39/2 = 487 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(39, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(39, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 243 / 8 ~ 30 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (487000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_500_500_250)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 25 (40 MHz * 25/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(25, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1)
#else
// DIV_INT = 40 (25 MHz * 40/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(40, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (500000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_500_250_250)
// CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 2, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 25 (40 MHz * 25/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(25, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1)
#else
// DIV_INT = 40 (25 MHz * 40/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(40, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (500000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_520_520_260)
// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 26 (40 MHz * 26/2 = 520 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(26, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1)
#else
#define FREQUENCY_NOT_SUPPORTED
#endif
// CLOCK_DIVIDER = 3 (SPI clock = 260 / 8 ~ 32 MHz)
- #define AR7240_SPI_CONTROL 0x43
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
#define CFG_HZ_FALLBACK (520000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_525_262_131)
// CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 2, 4)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
#if CONFIG_40MHZ_XTAL_SUPPORT
#define FREQUENCY_NOT_SUPPORTED
#else
// DIV_INT = 42 (25 MHz * 42/2 = 525 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(42, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(42, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 33 MHz)
- #define AR7240_SPI_CONTROL 0x41
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
#define CFG_HZ_FALLBACK (525000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_560_280_140)
// CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 2, 4)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 28 (40 MHz * 28/2 = 560 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(28, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1)
#else
// DIV_INT = 45 (25 MHz * 45/2 = 562 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(45, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(45, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 1 (SPI clock = 140 / 4 ~ 35 MHz)
- #define AR7240_SPI_CONTROL 0x41
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
#define CFG_HZ_FALLBACK (560000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_580_290_145)
// CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 2, 4)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 29 (40 MHz * 29/2 = 580 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(29, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1)
#else
#define FREQUENCY_NOT_SUPPORTED
#endif
// CLOCK_DIVIDER = 1 (SPI clock = 145 / 4 ~ 36 MHz)
- #define AR7240_SPI_CONTROL 0x41
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
#define CFG_HZ_FALLBACK (580000000LU/2)
#elif (CFG_PLL_FREQ == CFG_PLL_600_300_200)
// CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 3
- #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 2, 3)
+ #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 3)
#if CONFIG_40MHZ_XTAL_SUPPORT
// DIV_INT = 30 (40 MHz * 30/2 = 600 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(30, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(30, 1, 0, 1)
#else
// DIV_INT = 48 (25 MHz * 48/2 = 600 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_CPU_PLL_CONFIG_VAL(48, 1, 0, 1)
+ #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(48, 1, 0, 1)
#endif
// CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
- #define AR7240_SPI_CONTROL 0x42
+ #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
#define CFG_HZ_FALLBACK (600000000LU/2)
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