* Copyright (C) Linux Networx.
* Massive upgrade to work with the new intel gigabit NICs.
* <ebiederman at lnxi dot com>
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc.
*/
#include "e1000.h"
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
if (hw->mac_type == e1000_ich8lan)
return FALSE;
- if (hw->mac_type == e1000_82573) {
+ if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
eecd = E1000_READ_REG(hw, EECD);
/* Isolate bits 15 & 16 */
return -E1000_ERR_SWFW_SYNC;
eecd = E1000_READ_REG(hw, EECD);
- if (hw->mac_type != e1000_82573) {
+ if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
/* Request EEPROM Access */
if (hw->mac_type > e1000_82544) {
eecd |= E1000_EECD_REQ;
eeprom->use_eewr = FALSE;
break;
case e1000_82573:
+ case e1000_82574:
eeprom->type = e1000_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
case E1000_DEV_ID_82573L:
hw->mac_type = e1000_82573;
break;
+ case E1000_DEV_ID_82574L:
+ hw->mac_type = e1000_82574;
+ break;
case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
E1000_WRITE_REG(hw, TARC1, reg_tarc1);
break;
case e1000_82573:
+ case e1000_82574:
reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
reg_ctrl_ext &= ~(1 << 23);
reg_ctrl_ext |= (1 << 22);
| E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_WRITE_REG(hw, TXDCTL1, ctrl);
break;
- }
-
- if (hw->mac_type == e1000_82573) {
- uint32_t gcr = E1000_READ_REG(hw, GCR);
- gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
- E1000_WRITE_REG(hw, GCR, gcr);
+ case e1000_82573:
+ case e1000_82574:
+ reg_data = E1000_READ_REG(hw, GCR);
+ reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
+ E1000_WRITE_REG(hw, GCR, reg_data);
}
#if 0
switch (hw->mac_type) {
case e1000_ich8lan:
case e1000_82573:
+ case e1000_82574:
hw->fc = e1000_fc_full;
break;
default:
hw->phy_type = e1000_phy_gg82563;
break;
}
+ case BME1000_E_PHY_ID:
+ hw->phy_type = e1000_phy_bm;
+ break;
/* Fall Through */
default:
/* Should never have loaded on this device */
if (hw->phy_id == M88E1111_I_PHY_ID)
match = TRUE;
break;
+ case e1000_82574:
+ if (hw->phy_id == BME1000_E_PHY_ID)
+ match = TRUE;
+ break;
case e1000_80003es2lan:
if (hw->phy_id == GG82563_E_PHY_ID)
match = TRUE;
break;
case e1000_ich8lan:
case e1000_82573:
+ case e1000_82574:
/* The STATUS_TBIMODE bit is reserved or reused
* for the this device.
*/
case e1000_82571:
case e1000_82572:
case e1000_82573:
+ case e1000_82574:
case e1000_80003es2lan:
hw->bus_type = e1000_bus_type_pci_express;
break;
Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
+ Copyright 2011 Freescale Semiconductor, Inc.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
e1000_82571,
e1000_82572,
e1000_82573,
+ e1000_82574,
e1000_80003es2lan,
e1000_ich8lan,
e1000_num_macs
e1000_phy_gg82563,
e1000_phy_igp_3,
e1000_phy_ife,
+ e1000_phy_bm,
e1000_phy_undefined = 0xFF
} e1000_phy_type;
#define E1000_DEV_ID_82573E 0x108B
#define E1000_DEV_ID_82573E_IAMT 0x108C
#define E1000_DEV_ID_82573L 0x109A
+#define E1000_DEV_ID_82574L 0x10D3
#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
#define L1LXT971A_PHY_ID 0x001378E0
#define GG82563_E_PHY_ID 0x01410CA0
+#define BME1000_E_PHY_ID 0x01410CB0
+
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
#define PHY_SOF 0x01