ARM: uniphier: remove bit field macros from sc64-regs.h

Starting from PXs3, the bit fields of  RSTCTRL, CLKCTRL registers
will change every SoC.  There is no more point to define bitfields
in the common header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
index 0266e7e66b79d849d29d1fdca11d59a004795e3f..a4b7419e5404f21cd8541874e4707a981c3b1978 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-ld11.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -40,7 +40,7 @@ void uniphier_ld11_clk_init(void)
                int ch;
 
                tmp = readl(SC_CLKCTRL4);
-               tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
+               tmp |= BIT(10) | BIT(8);        /* MIO, STDMAC */
                writel(tmp, SC_CLKCTRL4);
 
                for (ch = 0; ch < 3; ch++) {

diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index d0a51f239c3808c2beede8c86631089d3b5bed59..80efb4e4e37f48f27adb00fa3f0139f44eb8c5d6 100644 (file)
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -15,34 +15,16 @@
 #define SC_RSTCTRL             (SC_BASE_ADDR | 0x2000)
 #define SC_RSTCTRL3            (SC_BASE_ADDR | 0x2008)
 #define SC_RSTCTRL4            (SC_BASE_ADDR | 0x200c)
-#define   SC_RSTCTRL4_ETHER            (1 << 6)
-#define   SC_RSTCTRL4_NAND             (1 << 0)
 #define SC_RSTCTRL5            (SC_BASE_ADDR | 0x2010)
 #define SC_RSTCTRL6            (SC_BASE_ADDR | 0x2014)
 #define SC_RSTCTRL7            (SC_BASE_ADDR | 0x2018)
-#define   SC_RSTCTRL7_UMCSB            (1 << 16)
-#define   SC_RSTCTRL7_UMCA2            (1 << 10)
-#define   SC_RSTCTRL7_UMCA1            (1 << 9)
-#define   SC_RSTCTRL7_UMCA0            (1 << 8)
-#define   SC_RSTCTRL7_UMC32            (1 << 2)
-#define   SC_RSTCTRL7_UMC31            (1 << 1)
-#define   SC_RSTCTRL7_UMC30            (1 << 0)
 
 #define SC_CLKCTRL             (SC_BASE_ADDR | 0x2100)
 #define SC_CLKCTRL3            (SC_BASE_ADDR | 0x2108)
 #define SC_CLKCTRL4            (SC_BASE_ADDR | 0x210c)
-#define   SC_CLKCTRL4_MIO              (1 << 10)
-#define   SC_CLKCTRL4_STDMAC           (1 << 8)
-#define   SC_CLKCTRL4_PERI             (1 << 7)
-#define   SC_CLKCTRL4_ETHER            (1 << 6)
-#define   SC_CLKCTRL4_NAND             (1 << 0)
 #define SC_CLKCTRL5            (SC_BASE_ADDR | 0x2110)
 #define SC_CLKCTRL6            (SC_BASE_ADDR | 0x2114)
 #define SC_CLKCTRL7            (SC_BASE_ADDR | 0x2118)
-#define   SC_CLKCTRL7_UMCSB            (1 << 16)
-#define   SC_CLKCTRL7_UMC32            (1 << 2)
-#define   SC_CLKCTRL7_UMC31            (1 << 1)
-#define   SC_CLKCTRL7_UMC30            (1 << 0)
 
 #define SC_CA72_GEARST         (SC_BASE_ADDR | 0x8000)
 #define SC_CA72_GEARSET                (SC_BASE_ADDR | 0x8004)