i.mx6q: mx6qsabrelite: Update the network configuration

Define CONFIG_PHY_MICREL, and
minimize the tx clock delay.

There is an issue with 1000 baseTx mode on early revs
of the SabreLite boards. The center tap pin 9 of the mag RJ45
USB combo was connected to the 3.3 filtered supply. Letting
this pin float solved the problem. Symptoms of the problem
were packets with many extra zeroes tacked on the end, and random
bit flips causing a high rate of CRC errors. 10/100 baseTx worked
fine on all revs. To disable 1000 baseTx for these boards, simply
define the environment variable disable_giga. ie.

setenv disable_giga 1

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 03a088a6a8afebc81ebb0786a744540bc1fb1ea0..f884bb53a091637d8e30ffbda3bfe17dbc80f0ad 100644 (file)
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -29,9 +29,9 @@
 #include <asm/gpio.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <micrel.h>
 #include <miiphy.h>
 #include <netdev.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
@@ -214,51 +214,32 @@ void setup_spi(void)
 }
 #endif
 
-#define MII_1000BASET_CTRL             0x9
-#define MII_EXTENDED_CTRL              0xb
-#define MII_EXTENDED_DATAW             0xc
-
-int fecmxc_mii_postcall(int phy)
+int board_phy_config(struct phy_device *phydev)
 {
-       /* prefer master mode */
-       miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
-
        /* min rx data delay */
-       miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105);
-       miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
-
-       /* max rx/tx clock delay, min rx/tx control delay */
-       miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104);
-       miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0);
-       miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x104);
-
+       ksz9021_phy_extended_write(phydev,
+                       MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+       /* min tx data delay */
+       ksz9021_phy_extended_write(phydev,
+                       MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+       /* max rx/tx clock delay, min rx/tx control */
+       ksz9021_phy_extended_write(phydev,
+                       MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+ 
        return 0;
 }
 
 int board_eth_init(bd_t *bis)
 {
-       struct eth_device *dev;
        int ret;
 
        setup_iomux_enet();
 
        ret = cpu_eth_init(bis);
-       if (ret) {
+       if (ret)
                printf("FEC MXC: %s:failed\n", __func__);
-               return ret;
-       }
-
-       dev = eth_get_dev_by_name("FEC");
-       if (!dev) {
-               printf("FEC MXC: Unable to get FEC device entry\n");
-               return -EINVAL;
-       }
-
-       ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-       if (ret) {
-               printf("FEC MXC: Unable to register FEC mii postcall\n");
-               return ret;
-       }
 
 #ifdef CONFIG_MXC_SPI
        setup_spi();

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 8a95af91ccd11a77bdb79b585945e30d6ff930f0..982f03f7104ecf58e5505c9c3c4216a1bc4cbf04 100644 (file)
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -77,6 +77,8 @@
 #define        CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_ETHPRIME                        "FEC"
 #define CONFIG_FEC_MXC_PHYADDR         6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE