Merge branch 'master' of git://git.denx.de/u-boot-socfpga

diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
new file mode 100644 (file)
index 0000000..6ff1ea6
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2014, 2020, Intel Corporation
+ */
+
+/ {
+       chosen {
+               tick-timer = &timer2;
+               u-boot,dm-pre-reloc;
+       };
+
+       memory@0 {
+               u-boot,dm-pre-reloc;
+       };
+
+       soc {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&clkmgr {
+       u-boot,dm-pre-reloc;
+
+       clocks {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&cb_intosc_hs_div2_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&cb_intosc_ls_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&f2s_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&gmac0 {
+       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+       altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+};
+
+&gmac1 {
+       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+       altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+};
+
+&gmac2 {
+       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+       altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
+};
+
+&i2c0 {
+       reset-names = "i2c";
+};
+
+&i2c1 {
+       reset-names = "i2c";
+};
+
+&i2c2 {
+       reset-names = "i2c";
+};
+
+&i2c3 {
+       reset-names = "i2c";
+};
+
+&i2c4 {
+       reset-names = "i2c";
+};
+
+&L2 {
+       u-boot,dm-pre-reloc;
+};
+
+&l4_mp_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&l4_sys_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&main_pll {
+       u-boot,dm-pre-reloc;
+};
+
+&main_noc_base_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&osc1 {
+       u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&periph_pll {
+       u-boot,dm-pre-reloc;
+};
+
+&porta {
+       bank-name = "porta";
+};
+
+&portb {
+       bank-name = "portb";
+};
+
+&portc {
+       bank-name = "portc";
+};
+
+&rst {
+       u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+       u-boot,dm-pre-reloc;
+};
+
+&timer2 {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index cc529bcd115675a82efb94e2d9d631b08de06693..a598c7554266bf4c9063d78a0ebb16ecfbfa4de1 100644 (file)
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright Altera Corporation (C) 2014. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -21,11 +10,6 @@
        #address-cells = <1>;
        #size-cells = <1>;
 
-       chosen {
-               tick-timer = &timer2;
-               u-boot,dm-pre-reloc;
-       };
-
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -60,7 +44,6 @@
                device_type = "soc";
                interrupt-parent = <&intc>;
                ranges;
-               u-boot,dm-pre-reloc;
 
                amba {
                        compatible = "simple-bus";
@@ -85,6 +68,8 @@
                                #dma-requests = <32>;
                                clocks = <&l4_main_clk>;
                                clock-names = "apb_pclk";
+                               resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
+                               reset-names = "dma", "dma-ocp";
                        };
                };
 
@@ -99,35 +84,29 @@
                clkmgr: clkmgr@ffd04000 {
                                compatible = "altr,clk-mgr";
                                reg = <0xffd04000 0x1000>;
-                               u-boot,dm-pre-reloc;
 
                                clocks {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
-                                       u-boot,dm-pre-reloc;
 
                                        cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        cb_intosc_ls_clk: cb_intosc_ls_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        f2s_free_clk: f2s_free_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        osc1: osc1 {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        main_pll: main_pll@40 {
@@ -138,7 +117,6 @@
                                                clocks = <&osc1>, <&cb_intosc_ls_clk>,
                                                         <&f2s_free_clk>;
                                                reg = <0x40>;
-                                               u-boot,dm-pre-reloc;
 
                                                main_mpu_base_clk: main_mpu_base_clk {
                                                        #clock-cells = <0>;
@@ -152,7 +130,6 @@
                                                        compatible = "altr,socfpga-a10-perip-clk";
                                                        clocks = <&main_pll>;
                                                        div-reg = <0x144 0 11>;
-                                                       u-boot,dm-pre-reloc;
                                                };
 
                                                main_emaca_clk: main_emaca_clk@68 {
@@ -228,7 +205,6 @@
                                                clocks = <&osc1>, <&cb_intosc_ls_clk>,
                                                         <&f2s_free_clk>, <&main_periph_ref_clk>;
                                                reg = <0xC0>;
-                                               u-boot,dm-pre-reloc;
 
                                                peri_mpu_base_clk: peri_mpu_base_clk {
                                                        #clock-cells = <0>;
@@ -242,7 +218,6 @@
                                                        compatible = "altr,socfpga-a10-perip-clk";
                                                        clocks = <&periph_pll>;
                                                        div-reg = <0x144 16 11>;
-                                                       u-boot,dm-pre-reloc;
                                                };
 
                                                peri_emaca_clk: peri_emaca_clk@e8 {
@@ -318,7 +293,6 @@
                                                         <&osc1>, <&cb_intosc_hs_div2_clk>,
                                                         <&f2s_free_clk>;
                                                reg = <0x64>;
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        s2f_user1_free_clk: s2f_user1_free_clk@104 {
@@ -345,7 +319,6 @@
                                                compatible = "altr,socfpga-a10-perip-clk";
                                                clocks = <&noc_free_clk>;
                                                fixed-divider = <4>;
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        l4_main_clk: l4_main_clk {
@@ -395,13 +368,28 @@
                                                clk-gate = <0xC8 11>;
                                        };
 
-                                       nand_clk: nand_clk {
+                                       nand_x_clk: nand_x_clk {
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-a10-gate-clk";
                                                clocks = <&l4_mp_clk>;
                                                clk-gate = <0xC8 10>;
                                        };
 
+                                       nand_ecc_clk: nand_ecc_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-a10-gate-clk";
+                                               clocks = <&nand_x_clk>;
+                                               clk-gate = <0xC8 10>;
+                                       };
+
+                                       nand_clk: nand_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-a10-gate-clk";
+                                               clocks = <&nand_x_clk>;
+                                               fixed-divider = <4>;
+                                               clk-gate = <0xC8 10>;
+                                       };
+
                                        spi_m_clk: spi_m_clk {
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-a10-gate-clk";
@@ -432,7 +420,7 @@
                };
 
                gmac0: ethernet@ff800000 {
-                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+                       compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
                        altr,sysmgr-syscon = <&sysmgr 0x44 0>;
                        reg = <0xff800000 0x2000>;
                        interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -452,8 +440,8 @@
                };
 
                gmac1: ethernet@ff802000 {
-                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
-                       altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+                       compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
+                       altr,sysmgr-syscon = <&sysmgr 0x48 8>;
                        reg = <0xff802000 0x2000>;
                        interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "macirq";
@@ -472,8 +460,8 @@
                };
 
                gmac2: ethernet@ff804000 {
-                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
-                       altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
+                       compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
+                       altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
                        reg = <0xff804000 0x2000>;
                        interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "macirq";
@@ -496,11 +484,11 @@
                        #size-cells = <0>;
                        compatible = "snps,dw-apb-gpio";
                        reg = <0xffc02900 0x100>;
+                       resets = <&rst GPIO0_RESET>;
                        status = "disabled";
 
                        porta: gpio-controller@0 {
                                compatible = "snps,dw-apb-gpio-port";
-                               bank-name = "porta";
                                gpio-controller;
                                #gpio-cells = <2>;
                                snps,nr-gpios = <29>;
@@ -516,11 +504,11 @@
                        #size-cells = <0>;
                        compatible = "snps,dw-apb-gpio";
                        reg = <0xffc02a00 0x100>;
+                       resets = <&rst GPIO1_RESET>;
                        status = "disabled";
 
                        portb: gpio-controller@0 {
                                compatible = "snps,dw-apb-gpio-port";
-                               bank-name = "portb";
                                gpio-controller;
                                #gpio-cells = <2>;
                                snps,nr-gpios = <29>;
@@ -536,11 +524,11 @@
                        #size-cells = <0>;
                        compatible = "snps,dw-apb-gpio";
                        reg = <0xffc02b00 0x100>;
+                       resets = <&rst GPIO2_RESET>;
                        status = "disabled";
 
                        portc: gpio-controller@0 {
                                compatible = "snps,dw-apb-gpio-port";
-                               bank-name = "portc";
                                gpio-controller;
                                #gpio-cells = <2>;
                                snps,nr-gpios = <27>;
@@ -568,7 +556,6 @@
                        interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C0_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -580,7 +567,6 @@
                        interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C1_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -592,7 +578,6 @@
                        interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C2_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -604,7 +589,6 @@
                        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C3_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -616,7 +600,19 @@
                        interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C4_RESET>;
-                       reset-names = "i2c";
+                       status = "disabled";
+               };
+
+               spi0: spi@ffda4000 {
+                       compatible = "snps,dw-apb-ssi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xffda4000 0x100>;
+                       interrupts = <0 101 4>;
+                       num-cs = <4>;
+                       /*32bit_access;*/
+                       clocks = <&spi_m_clk>;
+                       resets = <&rst SPIM0_RESET>;
                        status = "disabled";
                };
 
@@ -626,16 +622,16 @@
                        #size-cells = <0>;
                        reg = <0xffda5000 0x100>;
                        interrupts = <0 102 4>;
-                       num-chipselect = <4>;
-                       bus-num = <0>;
+                       num-cs = <4>;
                        /*32bit_access;*/
                        tx-dma-channel = <&pdma 16>;
                        rx-dma-channel = <&pdma 17>;
                        clocks = <&spi_m_clk>;
+                       resets = <&rst SPIM1_RESET>;
                        status = "disabled";
                };
 
-               sdr: sdr@ffc25000 {
+               sdr: sdr@ffcfb100 {
                        compatible = "altr,sdr-ctl", "syscon";
                        reg = <0xffcfb100 0x80>;
                };
@@ -666,14 +662,14 @@
 
                nand: nand@ffb90000 {
                        #address-cells = <1>;
-                       #size-cells = <1>;
-                       compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
-                       reg = <0xffb90000 0x20>,
-                             <0xffb80000 0x1000>;
+                       #size-cells = <0>;
+                       compatible = "altr,socfpga-denali-nand";
+                       reg = <0xffb90000 0x72000>,
+                             <0xffb80000 0x10000>;
                        reg-names = "nand_data", "denali_reg";
                        interrupts = <0 99 4>;
-                       dma-mask = <0xffffffff>;
-                       clocks = <&nand_clk>;
+                       clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+                       clock-names = "nand", "nand_x", "ecc";
                        resets = <&rst NAND_RESET>;
                        status = "disabled";
                };
@@ -759,6 +755,8 @@
                        cdns,fifo-width = <4>;
                        cdns,trigger-address = <0x00000000>;
                        clocks = <&qspi_clk>;
+                       resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
+                       reset-names = "qspi", "qspi-ocp";
                        status = "disabled";
                };
 
@@ -767,7 +765,6 @@
                        compatible = "altr,rst-mgr";
                        reg = <0xffd05000 0x100>;
                        altr,modrst-offset = <0x20>;
-                       u-boot,dm-pre-reloc;
                };
 
                scu: snoop-control-unit@ffffc000 {
@@ -785,7 +782,7 @@
                timer@ffffc600 {
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xffffc600 0x100>;
-                       interrupts = <1 13 0xf04>;
+                       interrupts = <1 13 0xf01>;
                        clocks = <&mpu_periph_clk>;
                };
 
@@ -795,6 +792,8 @@
                        reg = <0xffc02700 0x100>;
                        clocks = <&l4_sp_clk>;
                        clock-names = "timer";
+                       resets = <&rst SPTIMER0_RESET>;
+                       reset-names = "timer";
                };
 
                timer1: timer1@ffc02800 {
@@ -803,6 +802,8 @@
                        reg = <0xffc02800 0x100>;
                        clocks = <&l4_sp_clk>;
                        clock-names = "timer";
+                       resets = <&rst SPTIMER1_RESET>;
+                       reset-names = "timer";
                };
 
                timer2: timer2@ffd00000 {
@@ -811,7 +812,8 @@
                        reg = <0xffd00000 0x100>;
                        clocks = <&l4_sys_free_clk>;
                        clock-names = "timer";
-                       u-boot,dm-pre-reloc;
+                       resets = <&rst L4SYSTIMER0_RESET>;
+                       reset-names = "timer";
                };
 
                timer3: timer3@ffd00100 {
@@ -820,6 +822,8 @@
                        reg = <0xffd01000 0x100>;
                        clocks = <&l4_sys_free_clk>;
                        clock-names = "timer";
+                       resets = <&rst L4SYSTIMER1_RESET>;
+                       reset-names = "timer";
                };
 
                uart0: serial0@ffc02000 {
@@ -881,6 +885,7 @@
                        reg = <0xffd00200 0x100>;
                        interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sys_free_clk>;
+                       resets = <&rst L4WD0_RESET>;
                        status = "disabled";
                };
 
@@ -889,6 +894,7 @@
                        reg = <0xffd00300 0x100>;
                        interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sys_free_clk>;
+                       resets = <&rst L4WD1_RESET>;
                        status = "disabled";
                };
        };

diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
new file mode 100644 (file)
index 0000000..58cd497
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015, 2020 Intel. All rights reserved.
+ */
+
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+       aliases {
+               bootargs = "console=ttyS0,115200";
+               i2c0 = &i2c1;
+       };
+};
+
+&uart1 {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index ef10708ee867a811afc8d371a27ea3cdb7b922f9..0efbeccc5cd2cde7758869749ec91799bf0cd0a8 100644 (file)
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -1,20 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
-
 #include "socfpga_arria10.dtsi"
 
 / {
@@ -24,7 +11,6 @@
        aliases {
                ethernet0 = &gmac0;
                serial0 = &uart1;
-               i2c0 = &i2c1;
        };
 
        chosen {
@@ -36,7 +22,6 @@
                name = "memory";
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
-               u-boot,dm-pre-reloc;
        };
 
        a10leds {
@@ -63,8 +48,21 @@
                };
        };
 
+       ref_033v: 033-v-ref {
+               compatible = "regulator-fixed";
+               regulator-name = "0.33V";
+               regulator-min-microvolt = <330000>;
+               regulator-max-microvolt = <330000>;
+       };
+
        soc {
-               u-boot,dm-pre-reloc;
+               clkmgr@ffd04000 {
+                       clocks {
+                               osc1 {
+                                       clock-frequency = <25000000>;
+                               };
+                       };
+               };
        };
 };
 
@@ -137,6 +135,18 @@
        i2c-sda-falling-time-ns = <6000>;
        i2c-scl-falling-time-ns = <6000>;
 
+       adc@14 {
+               compatible = "lltc,ltc2497";
+               reg = <0x14>;
+               vref-supply = <&ref_033v>;
+       };
+
+       adc@16 {
+               compatible = "lltc,ltc2497";
+               reg = <0x16>;
+               vref-supply = <&ref_033v>;
+       };
+
        eeprom@51 {
                compatible = "atmel,24c32";
                reg = <0x51>;
@@ -155,7 +165,6 @@
 };
 
 &uart1 {
-       u-boot,dm-pre-reloc;
        status = "okay";
 };
 
@@ -167,24 +176,3 @@
 &watchdog1 {
        status = "okay";
 };
-
-/* Clock available early */
-&main_periph_ref_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&l4_mp_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&l4_sp_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&clkmgr {
-       u-boot,dm-pre-reloc;
-};
-
-&sysmgr {
-       u-boot,dm-pre-reloc;
-};

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
new file mode 100644 (file)
index 0000000..c229e82
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2015, 2020 Intel. All rights reserved.
+ */
+
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_socdk-u-boot.dtsi"
+
+/ {
+       chosen {
+               firmware-loader = <&fs_loader0>;
+       };
+
+       fs_loader0: fs-loader {
+               u-boot,dm-pre-reloc;
+               compatible = "u-boot,fs-loader";
+               phandlepart = <&mmc 1>;
+       };
+};
+
+&fpga_mgr {
+       u-boot,dm-pre-reloc;
+       altr,bitstream = "fit_spl_fpga.itb";
+};
+
+&mmc {
+       u-boot,dm-pre-reloc;
+};
+
+/* Clock available early */
+&main_sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index d6b6c2ddc0914409aabd2e85ce198b6741a049c7..64dc0799f3d763f7bee548b644b841acc7ca2aa0 100644 (file)
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -1,47 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 /dts-v1/;
 #include "socfpga_arria10_socdk.dtsi"
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
-#include "socfpga_arria10_handoff_u-boot.dtsi"
-
-/ {
-       chosen {
-               firmware-loader = <&fs_loader0>;
-       };
-
-       fs_loader0: fs-loader {
-               u-boot,dm-pre-reloc;
-               compatible = "u-boot,fs-loader";
-               phandlepart = <&mmc 1>;
-       };
-};
-
-&fpga_mgr {
-       u-boot,dm-pre-reloc;
-       altr,bitstream = "fit_spl_fpga.itb";
-};
 
 &mmc {
-       u-boot,dm-pre-reloc;
        status = "okay";
-       num-slots = <1>;
        cap-sd-highspeed;
+       cap-mmc-highspeed;
        broken-cd;
        bus-width = <4>;
 };
@@ -57,20 +25,3 @@
                             <48 IRQ_TYPE_LEVEL_HIGH>;
        };
 };
-
-/* Clock available early */
-&main_sdmmc_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&peri_sdmmc_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&sdmmc_free_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&sdmmc_clk {
-       u-boot,dm-pre-reloc;
-};

diff --git a/arch/arm/dts/socfpga_arria5_secu1.dts b/arch/arm/dts/socfpga_arria5_secu1.dts
index dadf766682d8dd45dd20b93c010f01b9c90391d9..820e29ad6d40db6a754a8de8622a25ced4737eca 100644 (file)
--- a/arch/arm/dts/socfpga_arria5_secu1.dts
+++ b/arch/arm/dts/socfpga_arria5_secu1.dts
@@ -31,6 +31,12 @@
                spi0 = &spi1;
        };
 
+       bootcount@0 {
+               compatible = "u-boot,bootcount-rtc";
+               rtc = <&rtc>;
+               offset = <0x9e>;
+       };
+
        i2c_gpio: i2c@0 {
                compatible = "i2c-gpio";
                #address-cells = <1>;

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 38d6c1b2ba32bb9e03b2b53f81e6d69d27e0e027..a3699e82a19e6edd475aef43179a6de1b0df84b6 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -46,6 +46,7 @@ config TARGET_SOCFPGA_ARRIA10
        bool
        select SPL_ALTERA_SDRAM
        select SPL_BOARD_INIT if SPL
+       select SPL_CACHE if SPL
        select CLK
        select SPL_CLK if SPL
        select DM_I2C

diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index 230959ec8659597248ac4dd70b22cf1a813cfab1..fcb38f1a41082ca88e09e9026b63176e8c3df776 100644 (file)
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -48,6 +48,9 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 # CONFIG_SPL_BLK is not set
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_DM_BOOTCOUNT_RTC=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -76,6 +79,8 @@ CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
 CONFIG_SPI=y
 CONFIG_SPI_MEM=y
 CONFIG_DESIGNWARE_SPI=y