armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_ID
authorAshish Kumar <Ashish.Kumar@nxp.com>
Thu, 12 Oct 2017 09:51:54 +0000 (15:21 +0530)
committerYork Sun <york.sun@nxp.com>
Fri, 27 Oct 2017 15:41:12 +0000 (08:41 -0700)
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.

These change where introduced in phy driver in commit 05b29aa0cb68
("net: phy: realtek: fix enabling of the TX-delay for RTL8211F").

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
board/freescale/ls1088a/eth_ls1088aqds.c
drivers/net/ldpaa_eth/ls1088a.c

index de70aee867776a0824e258f1b6a530906a39a02f..7fe446e624c0b2bd786c371d77e89d3b42b32f81 100644 (file)
@@ -634,6 +634,7 @@ int board_eth_init(bd_t *bis)
        for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
                switch (wriop_get_enet_if(i)) {
                case PHY_INTERFACE_MODE_RGMII:
+               case PHY_INTERFACE_MODE_RGMII_ID:
                        ls1088a_handle_phy_interface_rgmii(i);
                        break;
                case PHY_INTERFACE_MODE_QSGMII:
index 061935e51c555f4ec7f71878486dac1ffe3487e8..780a23998ad944dcc2c4bfc25eb59627852f4bb0 100644 (file)
@@ -99,7 +99,7 @@ void fsl_rgmii_init(void)
        ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
 
        if (!ec)
-               wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
+               wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
 #endif
 
 #ifdef CONFIG_SYS_FSL_EC2
@@ -108,7 +108,7 @@ void fsl_rgmii_init(void)
        ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
 
        if (!ec)
-               wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
+               wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
 #endif
 }
 #endif