sbc8548: relocate fixed ddr init code to ddr.c file

Nothing to see here, just a relocation of the fixed ddr init
sequence to live in the actual ddr.c file itself.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 996ffe206da7bb31a7f3228c84b359709dfaa120..0d9a1ba62b7e6a02471cc7a716cf8ff4ac55e246 100644 (file)
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -54,3 +54,51 @@ void fsl_ddr_board_options(memctl_options_t *popts,
         */
        popts->half_strength_driver_enable = 0;
 }
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ *  fixed_sdram init -- doesn't use serial presence detect.
+ *  Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ */
+phys_size_t fixed_sdram(void)
+{
+       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+       out_be32(&ddr->cs0_bnds,        0x0000007f);
+       out_be32(&ddr->cs1_bnds,        0x008000ff);
+       out_be32(&ddr->cs2_bnds,        0x00000000);
+       out_be32(&ddr->cs3_bnds,        0x00000000);
+
+       out_be32(&ddr->cs0_config,      0x80010101);
+       out_be32(&ddr->cs1_config,      0x80010101);
+       out_be32(&ddr->cs2_config,      0x00000000);
+       out_be32(&ddr->cs3_config,      0x00000000);
+
+       out_be32(&ddr->timing_cfg_3,    0x00000000);
+       out_be32(&ddr->timing_cfg_0,    0x00220802);
+       out_be32(&ddr->timing_cfg_1,    0x38377322);
+       out_be32(&ddr->timing_cfg_2,    0x0fa044C7);
+
+       out_be32(&ddr->sdram_cfg,       0x4300C000);
+       out_be32(&ddr->sdram_cfg_2,     0x24401000);
+
+       out_be32(&ddr->sdram_mode,      0x23C00542);
+       out_be32(&ddr->sdram_mode_2,    0x00000000);
+
+       out_be32(&ddr->sdram_interval,  0x05080100);
+       out_be32(&ddr->sdram_md_cntl,   0x00000000);
+       out_be32(&ddr->sdram_data_init, 0x00000000);
+       out_be32(&ddr->sdram_clk_cntl,  0x03800000);
+       asm("sync;isync;msync");
+       udelay(500);
+
+       #ifdef CONFIG_DDR_ECC
+         /* Enable ECC checking */
+         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
+       #else
+         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+       #endif
+
+       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif

diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 96554b2cdcc490442c63b9dcf0f708e946289c60..d1ef3bee50f9bc146b0758ada32ec7d2cf01487f 100644 (file)
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -219,50 +219,6 @@ testdram(void)
 }
 #endif
 
-#if !defined(CONFIG_SPD_EEPROM)
-#define CONFIG_SYS_DDR_CONTROL 0xc300c000
-/*************************************************************************
- *  fixed_sdram init -- doesn't use serial presence detect.
- *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
-       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
-       out_be32(&ddr->cs0_bnds, 0x0000007f);
-       out_be32(&ddr->cs1_bnds, 0x008000ff);
-       out_be32(&ddr->cs2_bnds, 0x00000000);
-       out_be32(&ddr->cs3_bnds, 0x00000000);
-       out_be32(&ddr->cs0_config, 0x80010101);
-       out_be32(&ddr->cs1_config, 0x80010101);
-       out_be32(&ddr->cs2_config, 0x00000000);
-       out_be32(&ddr->cs3_config, 0x00000000);
-       out_be32(&ddr->timing_cfg_3, 0x00000000);
-       out_be32(&ddr->timing_cfg_0, 0x00220802);
-       out_be32(&ddr->timing_cfg_1, 0x38377322);
-       out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
-       out_be32(&ddr->sdram_cfg, 0x4300C000);
-       out_be32(&ddr->sdram_cfg_2, 0x24401000);
-       out_be32(&ddr->sdram_mode, 0x23C00542);
-       out_be32(&ddr->sdram_mode_2, 0x00000000);
-       out_be32(&ddr->sdram_interval, 0x05080100);
-       out_be32(&ddr->sdram_md_cntl, 0x00000000);
-       out_be32(&ddr->sdram_data_init, 0x00000000);
-       out_be32(&ddr->sdram_clk_cntl, 0x03800000);
-       asm("sync;isync;msync");
-       udelay(500);
-
-       #if defined (CONFIG_DDR_ECC)
-         /* Enable ECC checking */
-         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
-       #else
-         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
-       #endif
-
-       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
-
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif /* CONFIG_PCI1 */

diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 44c75269ce66827b8b20f5afcfd9865528be221b..09245b5b0ca3febd4bf494f99dc9e7b559f92b4e 100644 (file)
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -148,6 +148,7 @@
  */
 #ifndef CONFIG_SPD_EEPROM
        #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
+       #define CONFIG_SYS_DDR_CONTROL  0xc300c000
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ