u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
};
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF 0
+#define SDIOCFG_DRVDN_SLWR 0
+#define SDIOCFG_DRVUP 0x24
+#define SDIOCFG_DRVDN 0x14
+
#endif /* _TEGRA114_GP_PADCTRL_H_ */
#include <common.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
#include "pinmux-config-dalmore.h"
/*
pinmux_config_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl));
}
DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
};
+
+static struct padctrl_config dalmore_padctrl[] = {
+ /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
+};
#endif /* PINMUX_CONFIG_COMMON_H */